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GS8672D19BE Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS8672D19BE
Beschreibung 72Mb SigmaQuad-II+ Burst of 4 ECCRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 28 Seiten
GS8672D19BE Datasheet, Funktion
GS8672D19/37BE-450/400/375/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaQuadTM-II+
Burst of 4 ECCRAMTM
450 MHz–300 MHz
1.8 V VDD
1.5 V I/O
Features
• 2.0 Clock Latency
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write Capability due to ECC
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) outputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 18Mb, 36Mb and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadECCRAM Overview
The GS8672D19/37BE are built in compliance with the
SigmaQuad-II+ ECCRAM pinout standard for Separate I/O
synchronous ECCRAMs. They are 75,497,472-bit (72Mb)
ECCRAMs. The GS8672D19/37BE SigmaQuad ECCRAMs
are just one element in a family of low power, low voltage
HSTL I/O ECCRAMs designed to operate at the speeds needed
to implement economical high performance networking
systems.
Clocking and Addressing Schemes
The GS8672D19/37BE SigmaQuad-II+ ECCRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 ECCRAM is always two address
pins less than the advertised index depth (e.g., the 4M x18 has
a 1M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable ECCRAMs with no On-Chip
ECC, which typically have an SER of 200 FITs/Mb or more.
SER quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
tKHKH
tKHQV
-450
2.2 ns
0.45 ns
Parameter Synopsis
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.02a 6/2013
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology






GS8672D19BE Datasheet, Funktion
GS8672D19/37BE-450/400/375/333/300
Power-Up Sequence for SigmaQuad-II+ ECCRAMs
SigmaQuad-II+ ECCRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
1. After power supplies power-up and clocks (K, K) are stablized, 163,840 cycles are required to set Output Driver
Impedance.
2. Thereafter, an additional 65,536 clock cycles are required to lock the DLL after it has been enabled.
3. Begin Read and Write operations.
For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
On-Chip Error Correction
SigmaQuad-II+ ECCRAMs implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on
each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9],
D/Q[26:18], or D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible
to the user).
The ECC algorithm neither corrects nor detects multi-bit errors. However, GSI ECCRAMs are architected in such a way that a
single SER event very rarely causes a multi-bit error across any given "transmitted data unit", where a "transmitted data unit"
represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-
bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb measured at sea level).
Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one "error bit" per eight "data bits", in any 9-bit
"data byte") for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such
error-bit allocation is unnecessary with ECCRAMs —the entire memory array can be utilized for data storage, effectively
providing 12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC.
Rev: 1.02a 6/2013
6/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page









GS8672D19BE pdf, datenblatt
GS8672D19/37BE-450/400/375/333/300
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
–0.5 to 2.4
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VREF Voltage in VREF Pins
–0.5 to VDDQ
V
VI/O Voltage on I/O Pins
–0.5 to VDDQ +0.5 (2.4 V max.)
V
VIN Voltage on Other Input Pins
–0.5 to VDDQ +0.5 (2.4 V max.)
V
IIN Input Current on Any Pin
+/–100
mA dc
IOUT Output Current on Any I/O Pin
+/–100
mA dc
TJ Maximum Junction Temperature
120 oC
TSTG Storage Temperature
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
Min. Typ. Max. Unit
Supply Voltage
VDD 1.7 1.8 1.9 V
I/O Supply Voltage
VDDQ
1.4 — 1.6 V
Reference Voltage
VREF
VDDQ/2 – 0.05
— VDDQ/2 + 0.05 V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Parameter
Symbol
Min. Typ. Max. Unit
Junction Temperature
(Commercial Range Versions)
TJ
0 25 85 C
Junction Temperature
(Industrial Range Versions)*
TJ
–40 25 100 C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.02a 6/2013
12/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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