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GS81314LQ19GK Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS81314LQ19GK
Beschreibung 144Mb SigmaQuad-IVe Burst of 2 Single-Bank ECCRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS81314LQ19GK Datasheet, Funktion
GS81314LQ19/37GK-933/800
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaQuad-IVe™
Burst of 2 Single-Bank ECCRAM™
Up to 933 MHz
1.2V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• Organized as a single logical memory bank
• 933 MHz maximum operating frequency
• 1.866 BT/s peak transaction rate (in billions per second)
• 134 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed DDR Address Bus
• Two operations - Read and Write - per clock cycle
• No address/bank restrictions on Read and Write ops
• Burst of 2 Read and Write operations
• 5 cycle Read Latency
• On-chip ECC with virtually zero SER
• Loopback signal timing training capability
• 1.2V ~ 1.3V nominal core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configuration registers
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IVeFamily Overview
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81314LQ19/37GK SigmaQuad-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IVe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-933
-800
Parameter Synopsis
Max Operating Frequency
933 MHz
800 MHz
Read Latency
5 cycles
5 cycles
VDD
1.25V to 1.35V
1.15V to 1.35V
Rev: 1.02 3/2016
1/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology






GS81314LQ19GK Datasheet, Funktion
GS81314LQ19/37GK-933/800
Initialization Summary
Prior to functional use, these devices must first be initialized and configured. The steps described below will ensure that the
internal logic has been properly reset, and that functional timing parameters have been configured appropriately.
Flow Chart
Power-Up
Reset SRAM
Wait for Calibrations
Enable PLL,
Wait for Lock
Training
Required?
Yes
No
Address / Control
Input Training
Read Data
Output Training
Write Data
Input Training
Additional
Configuration
Normal Operation
Yes Train No
Again?
Notes:
1. MZT[1:0] and PZT[1:0] mode pins are used to set the default ODT state of all
input groups at power-up, and whenever RST is asserted High. The ODT state
for each input group can be changed any time thereafter using Register Write
Mode to program certain bits in the Configuration Registers.
2. Calibrations are performed for driver impedance, ODT impedance, and the PLL
current source immediately after RST is de-asserted Low. The calibrations can
take up to 384K cycles total. See the Power-Up and Reset Requirements section
for more information.
3. The PLL can be enabled by the PLL pin, or by the PLL Enable (PLE) bit in the
Configuration Registers. See the PLL Operation section for more information.
4. If the PLE register bit is used to enable the PLL, then Register Write Mode will
likely have to be utilized in the “Asynchronous, Pre-Input Training” method in
order to change the state of the bit, since Address / Control Input Training has
not yet been performed. See the Configuration Registers section for more infor-
mation.
5. It can take up to 64K cycles for the PLL to lock after it has been enabled.
6. Special Loopback Modes are available in these devices to perform Address /
Control Input Training; they are selected and enabled via the Loopback Mode
Select (LBK[1:0]) and Loopback Mode Enable (LBKE) bits in the Configuration
Registers.
7. If Loopback Modes are used to perform Address / Control Input Training, then
Register Write Mode will likely have to be utilized in the “Asynchronous,
Pre-Input Training” method in order to change the states of the LBK[1:0] and
LBKE register bits.
8. Loopback Modes can also be used for Read Data Output Training, if desired.
See the Signal Timing Training and Loopback Mode sections for more informa-
tion.
9. “Additional Configuration” includes programming the Read Latency to 5 cycles
(which is required by these devices), and any other configuration changes
required by the system. Since this step is performed after Address / Control Input
Training, Register Write Mode can be utilized in the “Asynchronous, Post-Input
Training” method (or perhaps the “Synchronous” method, if the synchronous tim-
ing requirements can be met at the particular operating frequency).
10. It is up to the system to determine if/when re-training is necessary.
Rev: 1.02 3/2016
6/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology

6 Page









GS81314LQ19GK pdf, datenblatt
GS81314LQ19/37GK-933/800
Register Description
As described previously, Register Write Mode provides the ability to program up to sixteen distinct 6-bit configuration registers us-
ing SDR timing on the SA[10:1] address input pins. Specifically, SA[4:1] are used to select one of the sixteen distinct registers, and
SA[10:5] are used to program the six data bits of the selected register.
The registers are defined as follows:
Address
Pin
Bit Usage
Active
Active
Active
Active
Active
Unused
Active
SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1
8G 6G 8J 6J 8M 6M 8P 6P 8T 6T
Register Data Bits
Register Select Bits
DZT[1:0]
RLM
RSVD[2:0]
PLE
LBK[1:0]
LBKE
KDZT[1:0]
CKZT[1:0]
CZT[1:0]
AZT[1:0]
Reserved for GSI Internal Use Only
0000
0001
0010
0011
0100
All Others except “111X”
111X
Reg #
0
1
2
3
4
5 ~ 13
14 ~ 15
Notes:
1. Unused/unlabeled register bits should be written to “0”.
2. The RSVD[2:0] bits in Register #1 should be written to “100”.
3. Registers #14 and #15 are reserved for GSI internal use only. Users should not access these registers.
Register Bit Definitions
Read Latency Select
RLM
0 Read Latency = 5 cycles
1 reserved
1 POR/RST Default
PLL Enable
PLE
0 Disable PLL, if PLL pin = 0
1 Enable PLL
0 POR/RST Default
Note: The power-on / reset default value of the RLM register bit is “1”. Consequently, Register Write Mode must be used to set the
RLM bit to “0”, to program RL=5 in these devices, prior to issuing Read operations.
Rev: 1.02 3/2016
12/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology

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