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GS81313LD18GK Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS81313LD18GK
Beschreibung 144Mb SigmaQuad-IIIe Burst of 4 ECCRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 26 Seiten
GS81313LD18GK Datasheet, Funktion
GS81313LD18/36GK-833/714/625
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaQuad-IIIe™
Burst of 4 ECCRAM™
Up to 833 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• 833 MHz maximum operating frequency
• 833 MT/s peak transaction rate (in millions per second)
• 120 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 4 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.25V ~ 1.3V core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IIIeFamily Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81313LD18/36GK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g. the 8M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-833
-714
-625
Parameter Synopsis
Max Operating Frequency
833 MHz
714 MHz
625 MHz
Read Latency
3 cycles
3 cycles
3 cycles
VDD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.13 7/2016
1/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology






GS81313LD18GK Datasheet, Funktion
GS81313LD18/36GK-833/714/625
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The PLL is disabled.
• The states of R, and W control inputs are ignored.
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• Q are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 224K (229,376) cycles.
During this time:
• Driver and ODT impedances are calibrated. Can take up to 160K cycles.
• The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles.
Note: The PLL pin may be asserted High or de-asserted Low during this time. If asserted High, PLL synchronization begins
immediately after the current source for the PLL is calibrated. If de-asserted Low, PLL synchronization begins after the PLL pin is
asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert PLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles for the PLL to lock.
After the PLL has locked:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low (as in Step 4 above), Steps 5~7 above must be followed before Read and Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.13 7/2016
6/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

6 Page









GS81313LD18GK pdf, datenblatt
GS81313LD18/36GK-833/714/625
I/O Capacitance
Parameter
Input Capacitance
Output Capacitance
Notes:
1. VIN = VDDQ/2.
2. VOUT = VDDQ/2.
3. TA = 25C, f = 1 MHz.
Symbol
CIN
COUT
Min
Input Electrical Characteristics
Parameter
Symbol
Min
Typ
DC Input Reference Voltage
VREFdc
0.48 * VDDQ
0.50 * VDDQ
DC Input High Voltage (HS)
VIH1dc
VREF + 0.08
0.80 * VDDQ
DC Input Low Voltage (HS)
VIL1dc
-0.15
0.20 * VDDQ
DC Input High Voltage (LS)
VIH2dc
0.75 * VDDQ
VDDQ
DC Input Low Voltage (LS)
VIL2dc
-0.15
0
AC Input Reference Voltage
VREFac
0.47 * VDDQ
0.50 * VDDQ
AC Input High Voltage (HS)
VIH1ac
VREF + 0.15
0.80 * VDDQ
AC Input Low Voltage (HS)
VIL1ac
-0.25
0.20 * VDDQ
AC Input High Voltage (LS)
VIH2ac
VDDQ - 0.2
VDDQ
AC Input Low Voltage (LS)
VIL2ac
-0.25
0
Notes:
1. “Typ” parameter applies when Controller ROUTH = 40and SRAM RINH = RINL = 120.
2. “Typ” parameter applies when Controller ROUTL = 40and SRAM RINH = RINL = 120.
3. VREFac is equal to VREFdc plus noise.
4. VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
5. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
6. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W.
7. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.
Max Units Notes
5.0 pF 1, 3
5.5 pF 2, 3
Max
0.52 * VDDQ
VDDQ + 0.15
VREF - 0.08
VDDQ + 0.15
0.25 * VDDQ
0.53 * VDDQ
VDDQ + 0.25
VREF - 0.15
VDDQ + 0.25
0.2
Units
V
V
V
V
V
V
V
V
V
V
Notes
1, 6
2, 6
7
7
3
1, 4~6
2, 4~6
4, 7
4, 7
Rev: 1.13 7/2016
12/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

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