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GS81302Q37GE Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS81302Q37GE
Beschreibung 144Mb SigmaQuad-II+ Burst of 2 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 28 Seiten
GS81302Q37GE Datasheet, Funktion
GS81302Q07/10/19/37E-318/300/250/200
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaQuad-II+TM
Burst of 2 SRAM
318 MHz–200 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• 2.0 clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GS81302Q07/10/19/37E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302Q07/10/19/37E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302Q07/10/19/37E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-318
3.145 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
Rev: 1.02e 5/2012
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology






GS81302Q37GE Datasheet, Funktion
GS81302Q07/10/19/37E-318/300/250/200
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R
Synchronous Read
Input Active Low
W
Synchronous Write
Input Active Low
BW0–BW3
Synchronous Byte Writes
Input Active Low
NW0–NW1
Synchronous Nybble Writes
Input
Active Low
(x8 only)
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
Qn
Synchronous Data Outputs
Output
Dn
Synchronous Data Inputs
Input —
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
QVLD
Q Valid Output
Output
ODT
On-Die Termination
Input Active High
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K and K cannot be set to VREF voltage.
Rev: 1.02e 5/2012
6/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology

6 Page









GS81302Q37GE pdf, datenblatt
GS81302Q07/10/19/37E-318/300/250/200
Thermal Impedance
Package
Test PCB
Substrate
θ JA (C°/W)
Airflow = 0 m/s
θ JA (C°/W)
Airflow = 1 m/s
θ JA (C°/W)
Airflow = 2 m/s
θ JB (C°/W) θ JC (C°/W)
165 BGA
4-layer
16.4
13.4
12.4 8.6 1.2
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Input Reference Voltage
VREF
VDDQ /2 – 0.05
VDDQ /2 + 0.05
Input High Voltage
VIH1 VREF + 0.1
VDDQ + 0.3
Input Low Voltage
VIL1 –0.3
VREF – 0.1
Input High Voltage
VIH2 0.7 * VDDQ
VDDQ + 0.3
Input Low Voltage
VIL2 –0.3
0.3 * VDDQ
Notes:
1. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
2. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
3. Parameters apply to ZQ during JTAG boundary scan testing only.
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min Max
Input Reference Voltage
VREF
VDDQ /2 – 0.08 VDDQ /2 + 0.08
Input High Voltage
VIH1
VREF + 0.2
VDDQ + 0.5
Input Low Voltage
VIL1 –0.5 VREF – 0.2
Input High Voltage
VIH2
VDDQ – 0.2
VDDQ + 0.5
Input Low Voltage
VIL2 –0.5 0.2
Notes:
1. VIH(MAX) and VIL(MIN) apply for pulse widths less than one-quarter of the cycle time.
2. Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other.
3. Parameters apply to K, K, SA, D, R, W, BW during normal operation and JTAG boundary scan testing.
4. Parameters apply to Doff, ODT during normal operation and JTAG boundary scan testing.
5. Parameters apply to ZQ during JTAG boundary scan testing only.
Units
V
V
V
V
V
Units
V
V
V
V
V
Notes
1
1
2,3
2,3
Notes
1,2,3
1,2,3
4,5
4,5
Rev: 1.02e 5/2012
12/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2010, GSI Technology

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