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GS81313LT36GK Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS81313LT36GK
Beschreibung 144Mb SigmaDDR-IIIe Burst of 2 ECCRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 29 Seiten
GS81313LT36GK Datasheet, Funktion
GS81313LT18/36GK-833/714/625
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
Up to 833 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• 833 MHz maximum operating frequency
• 833 MT/s peak transaction rate (in millions per second)
• 60 Gb/s peak data bandwidth (in x36 devices)
• Common I/O DDR Data Bus
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 2 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.25V ~ 1.3V core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaDDR-IIIeFamily Overview
SigmaDDR-IIIe ECCRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81313LT18/36GK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-833
-714
-625
Parameter Synopsis
Max Operating Frequency
833 MHz
714 MHz
625 MHz
Read Latency
3 cycles
3 cycles
3 cycles
VDD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.13 7/2016
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology






GS81313LT36GK Datasheet, Funktion
GS81313LT18/36GK-833/714/625
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• The PLL is disabled.
• The states of LD, and R/W control inputs are ignored.
Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• DQ are placed in the non-Read state, and remain so until the first Read operation.
• QVLD are driven Low, and remain so until the first Read operation.
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 224K (229,376) cycles.
During this time:
• Driver and ODT impedances are calibrated. Can take up to 160K cycles.
• The current source for the PLL is calibrated (based on RCS pin). Can take up to 64K cycles.
Note: The PLL pin may be asserted High or de-asserted Low during this time. If asserted High, PLL synchronization begins
immediately after the current source for the PLL is calibrated. If de-asserted Low, PLL synchronization begins after the PLL pin is
asserted High (see Step 6). In either case, Step 7 must follow thereafter.
Step 6: Assert PLL pin High (if de-asserted Low).
Step 7: Wait at least 64K (65,536) cycles for the PLL to lock.
After the PLL has locked:
• CQ, CQ begin toggling within specification.
Step 8: Begin initiating Read and Write operations.
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low (as in Step 4 above), Steps 5~7 above must be followed before Read and Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.13 7/2016
6/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

6 Page









GS81313LT36GK pdf, datenblatt
GS81313LT18/36GK-833/714/625
Input Timing
These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various
synchronous inputs. Specifically:
CK latches all address (SA) inputs.
CK latches all control (LD, R/W) inputs.
KD[1:0] and KD[1:0] latch particular write data (DQ) inputs, as follows:
KD0 and KD0 latch DQ[17:0] in x36, and DQ[8:0] in x18.
KD1 and KD1 latch DQ[35:18] in x36, and DQ[17:9] in x18.
Output Timing
These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is
tightly aligned with read data in order to enable reliable source-synchronous data transmission.
These devices utilize a PLL to control output timing. When the PLL is enabled, it generates 0and 180phase clocks from CK
that control read data output clock (CQ, CQ), read data (DQ), and read data valid (QVLD) output timing, as follows:
CK+0generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive.
• .CK+180generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive.
Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations.
When the PLL is enabled, CQ is aligned to an internally-delayed version of CK. See the AC Timing Specifications for more
information.
CQ[1:0] and CQ[1:0] align with particular DQ and QVLD outputs, as follows:
CQ0 and CQ0 align with DQ[17:0], QVLD0 in x36 devices, and DQ[8:0], QVLD0 in x18 devices.
CQ1 and CQ1 align with DQ[35:18], QVLD1 in x36 devices, and DQ[17:9], QVLD0 in x18 devices.
Rev: 1.13 7/2016
12/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

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