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GS81302R09E Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS81302R09E
Beschreibung 144Mb SigmaDDR-II Burst of 4 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS81302R09E Datasheet, Funktion
GS81302R08/09/18/36E-375/350/333/300/250
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaDDRTM-II
Burst of 4 SRAM
375 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb
devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDRFamily Overview
The GS81302R08/09/18/36E are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302R08/09/18/36E SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302R08/09/18/36E SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 and A1 are used to initialize the pointers that control
the data multiplexer / de-multiplexer so the RAM can perform
"critical word first" operations. From an external address point
of view, regardless of the starting point, the data transfers
always follow the same linear sequence {00, 01, 10, 11} or
{01, 10, 11, 00} or {10, 11, 00, 01} or {11, 00, 01, 10} (where
the digits shown represent A1, A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B4 RAMs are two address pins less than the advertised index
depth (e.g., the 16M x 8 has a 4M addressable index, and A0
and A1 are not accessible address pins).
Parameter Synopsis
tKHKH
tKHQV
-375
2.66 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
Rev: 1.03b 12/2011
1/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology






GS81302R09E Datasheet, Funktion
GS81302R08/09/18/36E-375/350/333/300/250
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Synchronous Read/Write
Input
Read: Active High
Write: Active Low
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 only
NW0–NW1
Nybble Write Control Pin
Input
Active Low
x8 only
LD
Synchronous Load Pin
Input Active Low
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
C
Output Clock
Input Active High
C
Output Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
MCL
Must Connect Low
——
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. C, C, K, K cannot be set to VREF voltage.
3. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum and it cannot be connected to ground or left unconnected.
Rev: 1.03b 12/2011
6/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page









GS81302R09E pdf, datenblatt
GS81302R08/09/18/36E-375/350/333/300/250
x36 Byte Write Enable (BWn) Truth Table
BW0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
BW1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
BW2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
BW3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1
11
01
10
00
D0–D8
Don’t Care
Data In
Don’t Care
Data In
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1
11
01
10
00
D0–D3
Don’t Care
Data In
Don’t Care
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
D4–D7
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.03b 12/2011
12/35
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

12 Page





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