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GS81302T06E Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS81302T06E
Beschreibung 144Mb SigmaDDR-II+ Burst of 2 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 29 Seiten
GS81302T06E Datasheet, Funktion
GS81302T06/11/20/38E-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaDDRTM-II+
Burst of 2 SRAM
500 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaDDRTM Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDR-IIFamily Overview
The GS81302T06/11/20/38E are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302T06/11/20/38E SigmaDDR-II+
SRAMs are just one element in a family of low power, low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS81302T06/11/20/38E SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 8 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.03c 11/2011
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology






GS81302T06E Datasheet, Funktion
GS81302T06/11/20/38E-500/450/400/350
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Synchronous Read/Write
Input
High: Read
Low: Write
BW0–BW3
Synchronous Byte Writes
Input Active Low
LD
Synchronous Load Pin
Input Active Low
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
MCL
Must Connect Low
——
DQ
Data I/O
Input/Output
Three State
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 V or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
QVLD
Q Valid Output
Output
ODT
On-Die Termination
Input Active High
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K and K cannot be set to VREF voltage.
Rev: 1.03c 11/2011
6/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page









GS81302T06E pdf, datenblatt
GS81302T06/11/20/38E-500/450/400/350
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VREF Voltage in VREF Pins
–0.5 to VDDQ
V
VI/O Voltage on I/O Pins
–0.5 to VDDQ +0.5 (2.9 V max.)
V
VIN Voltage on Other Input Pins
–0.5 to VDDQ +0.5 (2.9 V max.)
V
VTIN Input Voltage (TCK, TMS, TDI)
–0.5 to VDDQ +0.5 (2.9V max.)
V
IIN Input Current on Any Pin
+/–100
mA dc
IOUT Output Current on Any I/O Pin
+/–100
mA dc
TJ Maximum Junction Temperature
125 oC
TSTG Storage Temperature
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
Min. Typ. Max. Unit
Supply Voltage
VDD
1.7
1.8 1.9
V
I/O Supply Voltage
VDDQ
1.4 — VDD V
Reference Voltage
VREF
VDDQ/2 – 0.05
— VDDQ/2 + 0.05 V
Note:.
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Parameter
Symbol
Min. Typ. Max. Unit
Junction Temperature
(Commercial Range Versions)
TJ
0 25 85 °C
Junction Temperature
(Industrial Range Versions)*
TJ
–40 25 100 °C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.03c 11/2011
12/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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