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GS81302D11GE-500I Schematic ( PDF Datasheet ) - GSI Technology

Teilenummer GS81302D11GE-500I
Beschreibung 144Mb SigmaQuad-II+ Burst of 4 SRAM
Hersteller GSI Technology
Logo GSI Technology Logo 




Gesamt 30 Seiten
GS81302D11GE-500I Datasheet, Funktion
GS81302D06/11/20/38E-500/450/400/350
165-Bump BGA
Commercial Temp
Industrial Temp
144Mb SigmaQuad-II+
Burst of 4 SRAM
500 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) intputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GS81302D06/11/20/38E are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302D06/11/20/38E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302D06/11/20/38E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 8 has a
4M addressable index).
tKHKH
tKHQV
Parameter Synopsis
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.05b 6/2014
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology






GS81302D11GE-500I Datasheet, Funktion
GS81302D06/11/20/38E-500/450/400/350
Pin Description Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R
Synchronous Read
Input Active Low
W
Synchronous Write
Input Active Low
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x18/x36 only
K
Input Clock
Input Active High
K
Input Clock
Input Active Low
TMS
Test Mode Select
Input —
TDI
Test Data Input
Input —
TCK
Test Clock Input
Input —
TDO
Test Data Output
Output
VREF
HSTL Input Reference Voltage
Input —
ZQ
Output Impedance Matching Input
Input
Qn
Synchronous Data Outputs
Output
Dn
Synchronous Data Inputs
Input —
Doff
Disable DLL when low
Input Active Low
CQ
Output Echo Clock
Output
CQ
Output Echo Clock
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.5 V or 1.8 V Nominal
VSS
Power Supply: Ground
Supply
QVLD
Q Valid Output
Output
ODT
On-Die Termination
Input Active High
NC
No Connect
——
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. K and K cannot be set to VREF voltage.
Rev: 1.05b 6/2014
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

6 Page









GS81302D11GE-500I pdf, datenblatt
GS81302D06/11/20/38E-500/450/400/350
Nybble Write Clock Truth Table
NW NW NW NW
Current Operation
DDDD
K
(tn+1)
T
K
(tn+1½)
T
K
(tn+2)
T
K
(tn+2½)
T
K
(tn)
Write
Dx stored if NWn = 0 in all four data transfers
K
(tn+1)
D0
K
(tn+1½)
D2
K
(tn+2)
D3
K
(tn+2½)
D4
T
F
F
F
Write
Dx stored if NWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if NWn = 0 in 3rd data transfer only
X
X D2 X
F
F
F
T
Write
Dx stored if NWn = 0 in 4th data transfer only
X
X
X D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1
11
01
10
00
D0–D3
Don’t Care
Data In
Don’t Care
Data In
D4–D7
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.05b 6/2014
12/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

12 Page





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