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Teilenummer | GD25LQ128C |
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Beschreibung | 1.8V Uniform Sector Dual and Quad Serial Flash | |
Hersteller | GigaDevice | |
Logo | ||
Gesamt 30 Seiten 1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128C
GD25LQ128C
DATASHEET
1
1.8V Uniform Sector
Dual and Quad Serial Flash
BLOCK DIAGRAM
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
GD25LQ128C
6
6 Page 1.8V Uniform Sector
Dual and Quad Serial Flash
GD25LQ128C
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are
unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One
Time Programmable, once its set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS1, SUS2 bit
The SUS1 and SUS2 bit are read only bit in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set
the SUS2 to 1). The SUS1 and SUS2 bit are cleared to 0 by Program/Erase Resume (7AH) command as well as a
power-down, power-up cycle.
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12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ GD25LQ128C Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
GD25LQ128C | 1.8V Uniform Sector Dual and Quad Serial Flash | ELM |
GD25LQ128C | 1.8V Uniform Sector Dual and Quad Serial Flash | GigaDevice |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |