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PE97240 Schematic ( PDF Datasheet ) - Peregrine Semiconductor

Teilenummer PE97240
Beschreibung Integer-N Frequency Synthesizer
Hersteller Peregrine Semiconductor
Logo Peregrine Semiconductor Logo 




Gesamt 21 Seiten
PE97240 Datasheet, Funktion
Product Description
Peregrine’s PE97240 is a radiation tolerant high-
performance Integer-N PLL capable of frequency
synthesis up to 5 GHz. The device is designed for
commercial space applications and optimized for
superior phase noise performance.
The PE97240 features a selectable prescaler
modulus of 5/6 or 10/11, counters and a phase
comparator as shown in Figure 1. Counter values are
programmable through either a serial interface or
directly hard-wired.
The PE97240 is available in a 44-lead CQFP and is
manufactured on Peregrine’s UltraCMOS® process, a
patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering excellent
RF performance and intrinsic radiation tolerance.
Figure 1. Functional Diagram
Product Specification
PE97240
Radiation Tolerant UltraCMOS®
Integer-N Frequency Synthesizer
for Low Phase Noise Applications
Features
 Frequency range
 5 GHz in 10/11 prescaler modulus
 4 GHz in 5/6 prescaler modulus
 Phase noise floor figure of merit:
–230 dBc/Hz
 Low power: 75 mA @ 2.7V
 Serial or direct mode access
 Packaged in a 44-lead CQFP
 100 kRad(Si) total dose
PE97240
Document No. DOC-15214-7 www.e2v-us.com
©2010-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 21






PE97240 Datasheet, Funktion
PE97240
Product Specification
Table 6. AC Characteristics @ VDD = 2.7V, –40 °C < TA < +85 °C, unless otherwise specified
Symbol
Parameter
Condition
Min Typ Max
Control interface and latches (see Figures 16 and 17)1
fClk Serial data clock frequency2
tClkH Serial clock HIGH time
10
30
tClkL Serial clock LOW time
tDSU SDATA set-up time after SCLK rising edge
tDHLD
SDATA hold time after SCLK rising edge
tPW S_WR pulse width
tCWR SCLK rising edge to S_WR rising edge
tCE SCLK falling edge to E_WR transition
tWRC S_WR falling edge to SCLK rising edge
tEC E_WR transition to SCLK rising edge
Main divider 5/6 (including prescaler)
30
10
10
30
30
30
30
30
FIN
PF_IN
Operating frequency
Input level range
External AC coupling
800 MHz–4 GHz
800
–53
4000
7
Main divider 10/11 (including prescaler)
FIN
PF_IN
Operating frequency
Input level range
External AC coupling
800 MHz–<4 GHz
4–5 GHz
800
–53
2
5000
7
7
Main divider (prescaler bypassed)
FIN Operating frequency
PF_IN
Input level range
Reference divider
External AC coupling
50
–53
800
7
FR Operating frequency
PF_R
Reference input power4
Phase detector
Single-ended input
–55
100
7
fc Comparison frequency
100
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
dBm
MHz
dBm
dBm
MHz
dBm
MHz
dBm
MHz
©2010-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 21
Document No. DOC-15214-7 UltraCMOS® RFIC Solutions

6 Page









PE97240 pdf, datenblatt
Functional Description
The PE97240 consists of a prescaler, counters, a
phase detector, and control logic. The dual
modulus prescaler divides the VCO frequency by
either 5/6 or 10/11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 21-bit register. An
additional counter (“A”) is used in the modulus
PE97240
Product Specification
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus or
hardwired directly to the pins. There are also
various operational and test modes and a lock
detect output.
Figure 16. Functional Block Diagram
VDD
FFINin
FFINin
Pre_5/6_Sel
SCLK
SDATA
S_WR
M(8:0)
A(3:0)
R(5:0)
Pre_En
Direct
FFRR
ENH
Input Buffer
Prescaler
5/6 or 10/11
Prescaler
Enable Select
MSEL
Primary
21-bit
Latch
Secondary
20-bit
Latch
Serial Mode
20
Direct Mode
20
Input Buffer
SCLK
SDATA
E_WR
Enh
Register
8-bit
8
Main
Counter
13
66
R Counter
8
GND
fp
Phase
fc Detector
MSEL
fp
fc
PD_U
PD_D
LD
Cext
Dout
©2010-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 21
Document No. DOC-15214-7 UltraCMOS® RFIC Solutions

12 Page





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