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PDF PE4312 Data sheet ( Hoja de datos )
| Número de pieza | PE4312 | |
| Descripción | RF Digital Step Attenuator | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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Product Description
The PE4312 is a 50Ω, HaRP™ technology-enhanced 6-bit
RF Digital Step Attenuator (DSA) designed for use in 3G/4G
wireless infrastructure and other high performance RF
applications.
This DSA is a pin-compatible upgraded version of the
PE4302 with higher linearity, improved attenuation accuracy
and faster switching speed. An integrated digital control
interface supports both serial and parallel programming of
the attenuation, including the capability to program an initial
attenuation state at power-up.
Covering a 31.5 dB attenuation range in 0.5 dB steps, it
maintains high linearity and low power consumption from
1 MHz through 4 GHz. PE4312 also features an external
negative supply option, and is offered in a 20-lead 4 × 4 mm
QFN package. In addition, no external blocking capacitors
are required if 0 VDC is present on the RF ports.
The PE4312 is manufactured on Peregrine’s UltraCMOS®
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate.
Peregrine’s HaRP™ technology enhancements deliver high
linearity and excellent harmonics performance. It is an
innovative feature of the UltraCMOS® process, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Figure 1. Functional Schematic Diagram
Switched Attenuator Array
RF Input
RF Output
Parallel Control 6
Serial Control 3
Power-Up Control 2
Control Logic Interface
DOC-02132
Product Specification
PE4312
UltraCMOS® RF Digital Step Attenuator
6-bit, 31.5 dB, 1 MHz–4 GHz
Features
Attenuation: 0.5 dB steps to 31.5 dB
Safe attenuation state transitions
Monotonicity: 0.5 dB up to 4 GHz
High attenuation accuracy
±(0.10 + 1% x Atten) @ 1 GHz
±(0.15 + 2% x Atten) @ 2.2 GHz
±(0.15 + 8% x Atten) @ 4 GHz
High linearity: +59 dBm IIP3
Wide power supply range of 2.3–5.5V
1.8V control logic compatible
105 °C operating temperature
Programming modes
Direct parallel
Latched parallel
Serial
Unique power-up state selection
Pin compatible to PE4302, PE4305
and PE4306
Figure 2. Package Type
20-lead 4 × 4 mm QFN
Document No. DOC-13514-6 │ www.psemi.com
©2013-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 13
1 page  
PE4312
Product Specification
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4312. The P/S bit provides this
selection, with P/S = LOW selecting the parallel
interface and P/S = HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of six CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 5 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 5) to latch the new attenuation state into
the device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Table 5. Truth Table*
P/S C16 C8 C4 C2 C1 C0.5 Attenuation State
0 0 0 0 0 0 0 Reference Loss
0000001
0.5 dB
0000010
1 dB
0000100
2 dB
0001000
4 dB
0010000
8 dB
0100000
16 dB
0111111
31.5 dB
Note: * Not all 64 possible combinations of C0.5–C16 are shown in table.
Serial Interface
The serial interface is a 6-bit serial-in, parallel-out
shift register buffered by a transparent latch. It is
controlled by three CMOS-compatible signals: Data,
Document No. DOC-13514-6 │ www.psemi.com
Clock, and Latch Enable (LE). The Data and Clock
inputs allow data to be serially entered into the shift
register, a process that is independent of the state of
the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The timing for this operation is defined by
Figure 5 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
Power-up Control Settings
The PE4312 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
When the attenuator powers up in Serial mode
(P/S = 1), the six control bits are set to whatever
data is present on the six parallel data inputs (C0.5
to C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
When the attenuator powers up in Parallel mode
(P/S = 0) with LE = 0, the control bits are
automatically set to one of four possible values.
These four values are selected by the two power-up
control bits, PUP1 and PUP2, as shown in Table 6
(Power-Up Truth Table, Parallel Mode).
Table 6. Parallel PUP Truth Table*
P/S LE PUP2 PUP1
00
00
0
1
0
0
00
0
1
00
1
01 X
1
X
Attenuation State
Reference Loss
8 dB
16 dB
31.5 dB
Defined by C0.5-C16
Note: * Power up with LE = 1 provides normal parallel operation with C0.5-C16,
and PUP1 and PUP2 are not active.
©2013-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 13
5 Page 
PE4312
Product Specification
Figure 26. Evaluation Board Schematic
Notes: 1. CAUTION: Contains parts and assemblies susceptible to damage by electrostatic discharge (ESD).
2. Install shunt connector on JP2, JP3 and JP4.
DOC-13527
Document No. DOC-13514-6 │ www.psemi.com
©2013-2016 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PE4312.PDF ] | |
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