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PDF ADuM3123 Data sheet ( Hoja de datos )
| Número de pieza | ADuM3123 | |
| Descripción | Isolated Precision Gate Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
4.0 A output short-circuit pulsed current
Isolated working voltage
Secondary side to input side: 537 V
High frequency operation: 1 MHz maximum
3.3 V to 5 V input logic
4.5 V to 18 V output drive
Undervoltage lockout (UVLO): 2.8 V VDD1
Precise timing characteristics
64 ns maximum isolator and driver propagation delay
Complementary metal oxide semiconductor (CMOS) input
logic levels
High common-mode transient immunity: >25 kV/μs
High junction temperature operation: 125°C
Default low output
Safety and regulatory approvals (pending)
UL recognition per UL 1577
3000 V rms for 1 minute SOIC long package
CSA Component Acceptance Notice 5A
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Maximum working insulation voltage (VIORM) = 560 V peak
Narrow body, 8-lead SOIC
APPLICATIONS
Switching power supplies
Isolated gate bipolar transistors (IGBT)/MOSFET gate drives
Industrial inverters
Isolated Precision Gate Driver,
4.0 A Output
ADuM3123
GENERAL DESCRIPTION
The ADuM31231 is a 4.0 A isolated, single channel driver that
employs Analog Devices, Inc., iCoupler® technology to provide
precision isolation. The ADuM3123 provides 3000 V rms
isolation in the narrow-body, 8-lead SOIC package. Combining
high speed CMOS and monolithic transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as the combination
of pulse transformers and gate drivers.
The ADuM3123 operates with an input supply ranging from
3.0 V to 5.5 V, providing compatibility with lower voltage
systems. In comparison to gate drivers employing high voltage
level translation methodologies, the ADuM3123 offers the
benefit of true, galvanic isolation between the input and the
output. The output can continuously operate up to 380 V rms
relative to the input.
As a result, the ADuM3123 provides reliable control over the
switching characteristics of IGBT/MOSFET configurations over
a wide range of positive and negative switching voltages.
VDD1 1
VI 2
DISABLE 3
FUNCTIONAL BLOCK DIAGRAM
ADuM3123
ENCODE
DECODE
GND1 4
8 VDD2
7 VO
6 NIC
5 GND2
NIC = NOT INTERNALLY CONNECTED
Figure 1.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADuM3123
Data Sheet
Parameter
SWITCHING SPECIFICATIONS
Pulse Width2
Maximum Data Rate3
Propagation Delay4
ADuM3123 A Grade
Propagation Delay Skew5
Output Rise Time/Fall Time (10% to 90%)
Supply Current
Dynamic Input
Dynamic Output
Refresh Rate
Symbol Min
PW
tDHL, tDLH
tPSK
tR/tF
50
1
19
25
1
IDDI(D)
IDDO(D)
fr
Typ Max
40 62
46 68
12
12 24
0.05
1.65
1.2
Unit
ns
MHz
ns
ns
ns
ns
Test Conditions/Comments
See Figure 17
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 4.5 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
mA/Mbps
mA/Mbps
Mbps
VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
1 Short-circuit duration less than 1 µs. Average power must conform to the limits shown in the Absolute Maximum Ratings section.
2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4 tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VO signal. tDLH propagation delay is
measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VO signal. See Figure 17 for waveforms of propagation delay
parameters.
5 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 17 for waveforms of propagation delay parameters.
Rev. 0 | Page 4 of 15
5 Page 
ADuM3123
TYPICAL PERFORMANCE CHARACTERISTICS
CH1 = VI (2V/DIV)
1
CH2 = VO (5V/DIV)
2
CH1 1MΩBW 500M
CH2 1MΩBW 500M
M50ns 5.0GSPS CH1 2.68V
50.0ns/DIV
Figure 4. Input to Output Waveform for 2 nF Load, 3.6 Ω Series Gate Resistor
with 12 V Output Supply
CH1 = VI (2V/DIV)
1
CH2 = VO (5V/DIV)
2
CH1 1MΩBW 500M
CH2 1MΩBW 500M
M50ns 5.0GSPS CH1 2.68V
50.0ns/DIV
Figure 5. Input to Output Waveform for 2 nF Load, 0 Ω Series Gate Resistor
with 12 V Output Supply
CH1 = VDISABLE (2V/DIV)
1
CH2 = VO (5V/DIV)
2
CH1 1MΩBW 500M
CH2 1MΩBW 500M
M50ns 5.0GSPS CH1 2.68V
Figure 6. DISABLE to Output Waveform for 2 nF Load, 3.6 Ω Resistor with
12 V Output Supply, VI = VDD1
Data Sheet
CH1 = VDD1 (2V/DIV)
1
CH2 = VO (5V/DIV)
2
CH1 1MΩBW 500M
CH2 1MΩBW 500M
M50ns 1.0GSPS CH1 1.36V
10.0µs/DIV
Figure 7. Typical VDD1 Delay to Output Waveform, VI = VDD1
3.0
2.5
2.0
VDD1 = 5.0V
1.5
1.0
VDD1 = 3.3V
0.5
0
0 0.25 0.50 0.75
FREQUENCY (MHz)
Figure 8. Typical IDD1 Current vs. Frequency
1.00
50
VDD2 = 15V
40 VDD2 = 10V
VDD2 = 5V
30
20
10
0
0
0.25
0.50
0.75
1.00
FREQUENCY (MHz)
Figure 9. Typical IDD2 Current vs. Frequency with 2 nF Load
Rev. 0 | Page 10 of 15
11 Page | ||
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