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PDF ADN8833 Data sheet ( Hoja de datos )
| Número de pieza | ADN8833 | |
| Descripción | 1A Thermoelectric Cooler (TEC) Driver | |
| Fabricantes | Analog Devices | |
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Data Sheet
Ultracompact, 1 A Thermoelectric Cooler
(TEC) Driver for Digital Control Systems
ADN8833
FEATURES
Patented high efficiency single inductor architecture
Integrated low RDSON MOSFETs for TEC driver
TEC voltage and current operation monitoring
No external sense resistor required
Independent TEC heating and cooling current limit settings
Programmable maximum TEC voltage
2 MHz PWM driver switching frequency
External synchronization
Digital thermal control loop compatible
2.50 V reference output with 1% accuracy
Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a
24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
TEC temperature control
Optical modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
VLIM/SD
ILIM
FUNCTIONAL BLOCK DIAGRAM
VTEC
ITEC
VDD
TEC CURRENT
AND VOLTAGE
SENSE AND LIMIT
ADN8833
LINEAR
POWER
STAGE
LDR
CONT
CONTROLLER
PWM
POWER
STAGE
PVIN
SW
VOLTAGE
REFERENCE
OSCILLATOR
AGND VREF
SFB
EN/SY
Figure 1.
PGNDx
GENERAL DESCRIPTION
The ADN8833 is a monolithic H-bridge TEC driver with
integrated 1 A power MOSFETs. It has a linear power stage with
the linear driver (LDR) output and a pulse-width modulation
(PWM) power stage with the SW output. Depending on the
control voltage at the CONT input, the ADN8833 drives current
through a TEC to settle the temperature of a laser diode or a passive
component attached to the TEC module to the programmed
target temperature.
The control voltage applied to the CONT input is generated by a
digital-to-analog converter (DAC) closing the digital proportional,
integral, derivative (PID) loop of temperature control system.
The internal 2.5 V reference voltage provides a 1% accurate
output that is used to bias a voltage divider network to program the
maximum TEC current and voltage limits for both the heating
and cooling modes. It can also be a reference voltage for the DAC
and the temperature sensing circuit, including a thermistor bridge
and an analog-to-digital converter (ADC).
Table 1. TEC Family Models
Model
MOSFET Thermal Loop
ADN8831 Discrete Digital/analog
ADN8833 Integrated Digital
ADN8834 Integrated Digital/analog
Package
LFCSP (CP-32-7)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADN8833
Parameter
P-MOSFET
N-MOSFET
SW Node Rise Time1
PWM Duty Cycle2
SFB Input Bias Current
PWM OSCILLATOR
Internal Oscillator Frequency
EN/SY Input Voltage
Low
High
External Synchronization Frequency
Synchronization Pulse Duty Cycle
EN/SY Rising to PWM Rising Delay
EN/SY to PWM Lock Time
EN/SY Input Current
Pull-Down Current
DRIVER CONTROL INPUT
Input Voltage Range
Input Resistance
Input Capacitance1
TEC CURRENT LIMIT
ILIM Input Voltage Range
Cooling
Heating
Current-Limit Threshold
Cooling
Heating
ILIM Input Current
Heating
Cooling
Cooling to Heating Current Detection
Threshold
TEC VOLTAGE LIMIT
Voltage Limit Gain
VLIM/SD Input Voltage Range1
VLIM/SD Input Current
Cooling
Heating
TEC CURRENT MEASUREMENT (WLCSP)
Current Sense Gain
Current Measurement Accuracy
ITEC Voltage Accuracy
Symbol
ISW_P_LKG
ISW_N_LKG
tSW_R
DSW
ISFB
fOSC
VEN/SY_ILOW
VEN/SY_IHIGH
fSYNC
DSYNC
tSYNC_PWM
tSY_LOCK
IEN/SY
VCONT
RCONT
CCONT
VILIMC
VILIMH
VILIMC_TH
VILIMH_TH
IILIMH
IILIMC
ICOOL_HEAT_TH
AVLIM
VVLIM
IILIMC
IILIMH
RCS
ILDR_ERROR
VITEC_@_700_mA
VITEC_@_−700_mA
VITEC_@_800_mA
VITEC_@_−800_mA
Test Conditions/Comments
CSW = 1 nF
EN/SY high
Min Typ
0.1
0.1
1
6
1
1.85 2.0
Number of SYNC cycles
2.1
1.85
10
50
0.3
0.3
0
40
40
VITEC = 0.5 V
VITEC = 2 V
Sourcing current
1.3
0.2
1.98 2.0
0.48 0.5
−0.2
37.5 40
40
(VLDR − VSFB)/VVLIM
2
0.2
VOUT2 < VVREF/2
VOUT2 > VVREF/2, sinking current
−0.2
8 10
VPVIN = 3.3 V
VPVIN = 5 V
700 mA ≤ ILDR ≤ 1 A, VPVIN = 3.3 V
800 mA ≤ ILDR ≤ 1 A, VPVIN = 5 V
VPVIN = 3.3 V, cooling, VVREF/2 + ILDR × RCS
VPVIN = 3.3 V, heating, VVREF/2 − ILDR × RCS
VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS
VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS
−10
−10
1.455
0.794
1.510
0.739
0.525
0.535
1.618
0.883
1.678
0.822
Data Sheet
Max Unit
10 µA
10 µA
ns
93 %
2 µA
2.15 MHz
0.8 V
V
3.25 MHz
90 %
ns
10 Cycles
0.5 µA
0.5 µA
VVREF
V
kΩ
pF
VVREF − 0.2
1.2
V
V
2.02 V
0.52 V
+0.2 µA
42.5 µA
mA
VVDD/2
+0.2
12.2
+10
+10
1.779
0.971
1.846
0.905
V/V
V
µA
µA
V/A
V/A
%
%
V
V
V
V
Rev. A | Page 4 of 23
5 Page 
ADN8833
EN
3
TEC CURRENT
4
LDO (TEC–)
PWM (TEC+)
1
CH1 1V CH2 1V
CH4 500mA Ω
CH3 2V
M20.0ms A CH3 800mV
T 40ms
Figure 16. Typical Enable Waveforms in Cooling Mode, VIN = 3.3 V,
Load = 2 Ω, TEC Current = 1 A
EN
3
TEC CURRENT
4
PWM (TEC–)
2
CH1 1V CH2 1V
CH4 500mA Ω
CH3 2V
LDO (TEC+)
M20.0ms A CH3 800mV
T 40ms
Figure 17. Enable Waveforms in Heating Mode, VIN = 3.3 V,
Load = 2 Ω, TEC Current = 1 A
T
SW
Data Sheet
3
LDO (TEC+)
1
PWM (TEC–)
2
CH1 20mV BW CH2 20mV BW M400ns A CH3
CH3 2.0V BW
T 0.0s
1.00V
Figure 18. Typical Switch and Voltage Ripple Waveforms in Cooling Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
T
SW
3
LDO (TEC+)
1
PWM (TEC–)
2
CH1 20mV BW CH2 20mV BW M400ns A CH3
CH3 2.0V BW
T 0.0s
1.00V
Figure 19. Typical Switch and Voltage Ripple Waveforms in Heating Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
Rev. A | Page 10 of 23
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADN8833.PDF ] | |
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