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ADN2905 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2905
Beschreibung CPRI and 10G Ethernet Data Recovery IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
ADN2905 Datasheet, Funktion
Data Sheet
CPRI and 10G Ethernet Data Recovery IC
with Amp/EQ from 614.4 Mbps to 10.3125 Gbps
ADN2905
FEATURES
GENERAL DESCRIPTION
Serial CPRI data rates
614.4 Mbps, 1.2288 Gbps, 2.4576 Gbps, 3.072 Gbps,
4.9152 Gbps, 6.144 Gbps, and 9.8304 Gbps
Ethernet data rates: 1.25 Gbps and 10.3125 Gbps
No reference clock required
Jitter performance superior to the SFF-8431 jitter specifications
Optional equalizer or 0 dB EQ input mode
Quantizer sensitivity: 200 mV p-p typical (equalizer mode)
Sample phase adjust (5.65 Gbps or greater)
Output polarity invert
I2C to access optional features
Loss of lock (LOL) indicator
PRBS generator/detector
Application aware power
349.5 mW at 9.8304 Gbps, 0 dB EQ input mode
287.7 mW at 6.144 Gbps, 0 dB EQ input mode
249.3 mW at 3.072 Gbps, 0 dB EQ input mode
Power supply: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V
4 mm × 4 mm, 24-lead LFCSP
APPLICATIONS
The ADN2905 provides the receiver functions of quantization and
multirate data recovery at 614.4 Mbps, 1.2288 Gbps, 1.25 Gbps,
2.4576 Gbps, 3.072 Gbps, 4.9152 Gbps, 6.144 Gbps, 9.8304 Gbps,
and 10.3125 Gbps, used in Common Public Radio Interface
(CPRI) and gigabit Ethernet applications. The ADN2905
automatically locks to all the specified CPRI and Ethernet data
rates without the need for an external reference clock or
programming. The ADN2905 jitter performance exceeds the
jitter requirement specified by SFF-8431.
The ADN2905 provides manual sample phase adjustment.
Additionally, the user can select an equalizer or a 0 dB EQ as the
input. The equalizer is either adaptive or can be manually set.
The ADN2905 also supports pseudorandom binary sequence
(PRBS) generation, bit error detection, and input data rate
readback features.
The ADN2905 is available in a compact 4 mm × 4 mm, 24-lead
chip scale package (LFCSP). All ADN2905 specifications are
defined over the ambient temperature range of −40°C to +85°C,
unless otherwise noted.
SFF-8431-compatible
Ethernet: 10GE, 1GE, and CPRI: OS/L.6 up to OS/L.96
FUNCTIONAL BLOCK DIAGRAM
SCK
SDA
LOL
REFCLKP/
REFCLKN
(OPTIONAL)
DATOUTP/
DATOUTN
I2C_ADDR
I2C REGISTERS
FREQUENCY
ACQUISITION
AND LOCK
DETECTOR
DATA RATE
ADN2905
CML
CLK
DDR
SAMPLE
PHASE
ADJUST
FIFO
÷N ÷2
PIN
2 0dB EQ
DATA
INPUT
NIN SAMPLER
50Ω 50Ω
EQ
I2C
VCM
VCC
FLOAT
I2C
RXD
RXCK
DOWNSAMPLER
AND LOOP
FILTER
PHASE
SHIFTER
DCO
CLOCK
Figure 1.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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ADN2905 Datasheet, Funktion
Data Sheet
ADN2905
OUTPUT AND TIMING SPECIFICATIONS
TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern =
PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted.
Table 3.
Parameter
CML OUTPUT CHARACTERISTICS
Data Differential Output Swing
Output Voltage
High
Low
CML OUTPUT TIMING CHARACTERISTICS
Rise Time
Fall Time
Setup Time, Full Rate Clock
Hold Time, Full Rate Clock
Setup Time, DDR Mode
Hold Time, DDR Mode
I2C INTERFACE DC CHARACTERISTICS
Input Voltage
High
Low
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time1
Stop Condition Setup Time
Bus Free Time Between Stop and
Start Conditions
LVTTL DC INPUT CHARACTERISITICS
(I2C_ADDR)
Input Voltage
High
Low
Input Current
High
Low
LVTTL DC OUTPUT CHARACTERISITICS
(LOS/LOL)
Output Voltage
High
Low
Symbol Test Conditions/Comments
9.8304 Gbps, DATA_SWING[3:0] = 0xC (default)
9.8304 Gbps, DATA_SWING[3:0] = 0xF (maximum)
9.8304 Gbps, DATA_SWING[3:0] = 0x4 (minimum)
VOH DC-coupled
VOL DC-coupled
tS
tH
tS
tH
VIH
VIL
VOL
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
tR/tF
tSU;STO
tBUF
20% to 80%, at 9.8304 Gbps, DATOUTN/DATOUTP
20% to 80%, at 9.8304 Gbps, CLKOUTN/CLKOUTP
80% to 20%, at 9.8304 Gbps, DATOUTN/DATOUTP
80% to 20%, at 9.8304 Gbps, CLKOUTN/CLKOUTP
See Figure 2
See Figure 2
See Figure 3
See Figure 3
LVTTL
VIN = 0.1 × VDD or VIN = 0.9 × VDD
IOL = 3.0 mA
See Figure 14
VIH
VIL
IIH VIN = 2.4 V
IIL VIN = 0.4 V
VOH IOH = 2.0 mA
VOL IOL = −2.0 mA
Min
535
668
189
VCC −
0.05
VCC −
0.36
17.4
22.2
17.5
23.9
2.0
−10.0
600
1300
600
600
100
300
20 +
0.1Cb
600
1300
2.0
−5
2.4
Typ
600
724
219
VCC −
0.025
VCC −
0.325
32.6
28.3
33
29.2
0.5
0.5
0.5
0.5
Max Unit
672 mV p-p
771 mV p-p
252 mV p-p
VCC
VCC −
0.29
V
V
46.5 ps
33.1 ps
49.1 ps
33.7 ps
UI
UI
UI
UI
0.8
+10.0
0.4
400
300
V
V
µA
V
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
0.8 V
5 µA
µA
V
0.4 V
Rev. A | Page 5 of 27

6 Page









ADN2905 pdf, datenblatt
Data Sheet
ADN2905
REGISTER MAP
Writing to register bits other than those clearly labeled is not recommended and may cause unintended results.
Table 7. Internal Register Map1, 2
Reg. Name
Addr. Default
R/W (Hex) (Hex)
Readback/Status
FREQMEAS0 R
0x0 N/A
FREQMEAS1 R
0x1 N/A
FREQMEAS2 R
0x2 N/A
FREQ_RB1 R
0x4 N/A
FREQ_RB2 R
0x5 N/A
STATUSA
R 0x6 N/A
General Control
CTRLA
R/W 0x8
0x10
CTRLB
R/W 0x9 0x08
CTRLC
R/W 0xA 0x05
FLL Control
LTR_MODE R/W 0xF
DPLL Control
DPLLA
R/W 0x10
DPLLD
R/W 0x13
0x00
0x1C
0x02
Phase
LA_EQ
R/W 0x14
R/W 0x16
0x00
0x08
Output Control
OUTPUTA
R/W 0x1E
0x00
OUTPUTB
R/W 0x1F
PRBS Control
PRBS Gen 1 R/W 0x39
0xCC
0x00
PRBS Gen 2
PRBS Gen 3
PRBS Gen 4
PRBS Gen 5
PRBS Gen 6
PRBS Rec 1
R/W 0x3A
R/W 0x3B
R/W 0x3C
R/W 0x3D
R/W 0x3E
R/W 0x3F
0x00
0x00
0x00
0x00
0x00
0x00
PRBS Rec 2
PRBS Rec 3
PRBS Rec 4
PRBS Rec 5
PRBS Rec 6
PRBS Rec 7
R
R
R
R
R
R
0x40
0x41
0x42
0x43
0x44
0x45
0x00
0x00
N/A
N/A
N/A
N/A
D7
X
X
0
SOFTWARE_
RESET
0
0
0
0
0
RX_TERM_
FLOAT
0
0
0
D6 D5 D4
D3 D2
D1 D0
FULLRATE
X
Reserved
FREQ0[7:0] (RATE_FREQ[7:0])
FREQ1[7:0] (RATE_FREQ[15:8])
FREQ2[7:0] (RATE_FREQ[23:16])
VCOSEL[7:0]
DIVRATE[3:0]
LOL status Reserved Static LOL
X
VCOSEL[9:8]
RATE_MEAS_
COMP
CDR_MODE[2:0]
0
INIT_FREQ
_ACQ
0
CDR
bypass
0
LOL config 1
00
Reset static
LOL
Reserved
RATE_
MEAS_EN
0
RATE_MEAS_
RESET
0
REFCLK_
PDN
0
1
LOL data
FREF_RANGE[1:0]
DATA_TO_REF_RATIO[3:0]
00
00
00
INPUT_SEL[1:0]
EDGE_SEL[1:0]
00
0
ADAPTIVE_
EQ_EN
TRANBW[2:0]
Reserved
to 0
DLL_SLEW[1:0]
SAMPLE_PHASE[3:0]
EQ_BOOST[3:0]
0 Data
squelch
DATA_SWING[3:0]
DATOUT_
DISABLE
1
DDR_
DISABLE
DATA_
POLARITY
Reserved
Reserved
0
DATA_ DATA_
0
DATA_
DATA_GEN_MODE[1:0]
CID_BIT CID_EN
GEN_EN
DATA_CID_LENGTH[7:0]
PROG_DATA[7:0]
PROG_DATA[15:8]
PROG_DATA[23:16]
PROG_DATA[31:24]
0 00
DATA_
RECEIVER_
CLEAR
DATA_
RECEIVER_
ENABLE
DATA_RECEIVER_
MODE[1:0]
PRBS_ERROR_COUNT[7:0]
PRBS_ERROR
DATA_LOADED[7:0]
DATA_LOADED[15:8]
DATA_LOADED[23:16]
DATA_LOADED[31:24]
Rev. A | Page 11 of 27

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