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PDF ADLD8403 Data sheet ( Hoja de datos )
| Número de pieza | ADLD8403 | |
| Descripción | Dual-Port ADSL/ADSL2+ Line Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Ultralow Power, Adaptive Linear Power,
Dual-Port ADSL/ADSL2+ Line Driver
ADLD8403
FEATURES
2 differential DSL channels comprising current feedback,
high output current amplifiers with integrated feedback
resistors plus biasing network
Ideal for use as ADSL/ADSL2+ dual-channel central office
(CO) line drivers
Low power consumption using Class H technology
Single 12.5 V supply operation
20.4 dBm line power, 1:1 transformer
Less than 600 mW per channel total power dissipation
while driving 20.4 dBm (includes 110 mW line power)
Less than 275 mW per channel total power dissipation
while driving 14.5 dBm (including line power)
High output voltage and current drive
43.4 V differential output voltage swing
Low distortion
−65 dBc typical multitone power ratio (MTPR) at 20.4 dBm,
26 kHz to 2.2 MHz
Low cost protection components enable ITU-T-K20 and
GR-1089 compliance
APPLICATIONS
ADSL/ADSL2+ CO line drivers
INTERNAL SCHEMATIC
VCC VCCP
INPA
VCOM_A
INNA
VCC
4kΩ
4kΩ
AV = 13V/V
VOPA
VONA
VEEP
Figure 1. Channel A Internal Schematic
GENERAL DESCRIPTION
The ADLD8403 comprises two differential, high output current,
low power consumption operational amplifiers. It is particularly
well suited for the CO driver interface in digital subscriber line
systems, such as ADSL and ADSL2+. The driver can deliver
20.4 dBm to a line while compensating for losses due to hybrid
insertion and back termination resistors. The ADLD8403 uses
the Analog Devices, Inc., second generation Adaptive Linear
Power™ (Class H) architecture to achieve unprecedented power
efficiency using a single power supply. Additional functionality
allows the shutdown of pumps for enhanced power savings for
line powers of less than 14.5 dBm. This functionality yields the
smallest printed circuit board (PCB) footprint and lowest total
cost of ownership.
The low power consumption, high output current, high
output voltage swing, and robust thermal packaging enable
the ADLD8403 to be the CO line driver in ADSL and other
xDSL systems.
The ADLD8403 is available in a 4 mm × 4 mm, 20-lead LFCSP.
18
14
10
6
2
–2
VOPA
VONB
VONA
VCCP
VOPB
–6
VEEP
0 1 2 3 4 5 6 7 8 9 10
TIME (µs)
Figure 2. Outputs and Pumps Time Domain Response, Typical ADSL/ADSL2+
Application Circuit, VCC = 12.5 V, POUT = 20.4 dBm, Crest Factor = 5.45
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADLD8403
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VCC
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
13.2 V
See Figure 3
−65°C to +150°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified in still air with the exposed pad soldered to a
4-layer JEDEC test board. θJC is specified at the exposed pad.
Table 3. Thermal Resistance
Package Type
20-Lead LFCSP (CP-20-10)
θJA
36.1
θJC
5.7
Unit
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADLD8403 is
limited by its junction temperature on the die.
The maximum safe junction temperature of plastic encapsulated
devices, as determined by the glass transition temperature of the
plastic, is 150°C. Exceeding this limit may temporarily cause a shift
in the parametric performance due to a change in the stresses
exerted on the die by the package. Exceeding this limit for an
extended period can result in device failure.
Data Sheet
Figure 3 shows the maximum power dissipation in the package vs.
the ambient temperature for the 20-lead LFCSP on a JEDEC
standard 4-layer board. θJA values are approximations.
6
TJ = 150°C
5
4
3
2
1
0
–25 –15 –5 5 15 25 35 45 55 65 75 85
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
for a 4-Layer Board
The power dissipated in the package (PD) is easily computed by
taking the total power consumed while driving a signal and
subtracting the power dissipated in the load. The total power
consumed is simply the product of the voltage between the
supply pins (VCC, VEEP, and VCCP) times the supply current (IS).
Use rms voltages and currents.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more copper in direct contact with the package leads
from PCB traces, through holes, ground, and power planes
reduces θJA.
ESD CAUTION
Rev. C | Page 4 of 10
5 Page 
ADLD8403
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.80
0.75
0.70
SEATING
PLANE
4.10
4.00 SQ
3.90
TOP VIEW
0.30
0.25
0.50
BSC
0.20
16
15
EXPOSED
PAD
20
1
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
5
11
0.50
0.40
10 6
BOTTOM VIEW
0.25 MIN
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 14. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
ADLD8403ACPZ-R2 −40°C to +85°C
ADLD8403ACPZ-R7 −40°C to +85°C
ADLD8403ACPZ-RL −40°C to +85°C
1 Z = RoHS Compliant Part.
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Data Sheet
Package Option
CP-20-10
CP-20-10
CP-20-10
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08848-0-9/14(C)
Rev. C | Page 10 of 10
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ADLD8403.PDF ] | |
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