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GS2972 Schematic ( PDF Datasheet ) - Semtech

Teilenummer GS2972
Beschreibung 3G/HD/SD-SDI Serializer
Hersteller Semtech
Logo Semtech Logo 




Gesamt 30 Seiten
GS2972 Datasheet, Funktion
GS2972
3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support
Key Features
• Operation at 2.970Gb/s, 2.970/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE ST 425 (Level A and Level B),
SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C and
DVB-ASI
• Integrated Cable Driver
• Integrated, low-noise VCO
• Integrated Narrow-Bandwidth PLL
• Integrated Audio Embedder for up to 8 channels of
48kHz audio
• Ancillary data insertion
• Optional conversion from SMPTE ST 425 Level A to
Level B for 1080p 50/60 4:2:2 10-bit
• Parallel data bus selectable as either 20-bit or 10-bit
• SMPTE video processing including TRS calculation and
insertion, line number calculation and insertion, line
based CRC calculation and insertion, illegal code
re-mapping, SMPTE ST 352 payload identifier
generation and insertion
• GSPI host interface
• +1.2V digital core power supply, +1.2V and +3.3V
analog power supplies, and selectable +1.8V or +3.3V
I/O power supply
• -20ºC to +85ºC operating temperature range
• Low power operation (typically at 400mW, including
Cable Driver)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and RoHS compliant
Applications
Application: 1080p 50/60 Camera/Camcorder
MIC
ADC
Audio
Processor
AUDIO 1/ 2
Audio Clocks
AES - IN
AUDIO 3/4
OPTICS
CCD
Video
Processor
20-bit
HV F/PCLK
GS2972
CTRL/TIME CODE
3G-SDI
Storage :
Tape/Disc /Solid State
HD-SDI
Link A
EQ
GS2974B
HD-SDI
Link B
EQ
GS2974B
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Deserializer
(GS1559 or
GS2970)
10-bit
HV F/PCLK
FIFO
WR
HD-SDI
Deserializer
(GS1559 or
GS2970)
10-bit
HV F/PCLK
FIFO
WR
10-bit
HV F/PCLK
10-bit
GS2972
3G-SDI
GS4910
HVF
X TAL
Application: Multi-format Audio Embedder Module
SD/HD/3G-SDI
EQ
GS2974B
GS2970
HVF
10-bit
P CLK
Audio Clocks
GS4911
GS2972
SD/HD/3G-SDI
AES
Audio
Inputs
Analog
Audio
Inputs
SRC
ADC
Switch
Logic
&
Buffers
AUDIO 1/ 2
AUDIO 3/ 4
AUDIO 5/ 6
AUDIO 7/ 8
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
1 of 125






GS2972 Datasheet, Funktion
4.7.17 Five-frame Sequence Detection - SD........................................................................ 57
4.7.18 Frame Sequence Detection - HD/3G ........................................................................ 60
4.7.19 ECC Error Detection and Correction ........................................................................ 61
4.7.20 Audio Control Packet Insertion - SD......................................................................... 61
4.7.21 Audio Control Packet Insertion - HD and 3G......................................................... 62
4.7.22 Audio Data Packet Insertion........................................................................................ 63
4.7.23 Audio Interrupt Control ................................................................................................ 64
4.8 ANC Data Insertion ....................................................................................................................... 65
4.8.1 ANC Insertion Operating Modes .................................................................................. 65
4.8.2 3G ANC Insertion............................................................................................................... 67
4.8.3 HD ANC Insertion.............................................................................................................. 69
4.8.4 SD ANC Insertion............................................................................................................... 70
4.9 Additional Processing Functions .............................................................................................. 71
4.9.1 Video Format Detection .................................................................................................. 71
4.9.2 3G Format Detection ........................................................................................................ 74
4.9.3 ANC Data Blanking ........................................................................................................... 75
4.9.4 ANC Data Checksum Calculation and Insertion..................................................... 75
4.9.5 TRS Generation and Insertion ....................................................................................... 75
4.9.6 HD and 3G Line Number Calculation and Insertion.............................................. 76
4.9.7 Illegal Code Re-Mapping................................................................................................. 76
4.9.8 SMPTE ST 352 Payload Identifier Packet Insertion ................................................ 77
4.9.9 Line Based CRC Generation and Insertion (HD/3G) .............................................. 78
4.9.10 EDH Generation and Insertion ................................................................................... 78
4.9.11 GS2972 3G/HD HANC Space Considerations when Embedding Audio ...... 79
4.9.12 SMPTE ST 372 Conversion ........................................................................................... 79
4.9.13 Processing Feature Disable.......................................................................................... 80
4.10 SMPTE ST 352 Data Extraction ............................................................................................... 81
4.11 Serial Clock PLL ........................................................................................................................... 82
4.11.1 PLL Bandwidth................................................................................................................. 82
4.11.2 Lock Detect........................................................................................................................ 83
4.12 Serial Digital Output .................................................................................................................. 84
4.12.1 Output Signal Interface Levels ................................................................................... 85
4.12.2 Overshoot/Undershoot ................................................................................................. 85
4.12.3 Slew Rate Selection......................................................................................................... 86
4.12.4 Serial Digital Output Mute ........................................................................................... 86
4.13 GSPI Host Interface ..................................................................................................................... 87
4.13.1 Command Word Description ...................................................................................... 88
4.13.2 Data Read or Write Access........................................................................................... 88
4.13.3 GSPI Timing....................................................................................................................... 89
4.14 Host Interface Register Maps .................................................................................................. 91
4.14.1 Video Core Registers...................................................................................................... 91
4.14.2 SD Audio Core................................................................................................................ 100
4.14.3 HD and 3G Audio Core Registers............................................................................. 111
4.15 JTAG ID Codeword ................................................................................................................... 119
4.16 JTAG Test Operation ................................................................................................................ 119
4.17 Device Power-Up ...................................................................................................................... 119
4.18 Device Reset ................................................................................................................................ 119
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
6 of 125

6 Page









GS2972 pdf, datenblatt
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
A4 H/HSYNC
A5, E1, G10,
K8
A6, B6
A7
A8
A9, D6, D7,
D8, F4
A10
CORE_VDD
PLL_VDD
LF
VBG
RSV
A_VDD
B4 PCLK
B5, C5, E2,
E5, E6, F5,
F6, G9
CORE_GND
Timing
Type
Description
Synch-
ronous
with
PCLK
Input
Input Power
Input Power
Analog
Output
Output
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
TIM_861 is LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set LOW.
Active Line Blanking
The H signal should be LOW for the active portion of the video line.
The signal goes LOW at the first active pixel of the line, and then
goes HIGH after the last active pixel of the line.
The H signal should be set HIGH for the entire horizontal blanking
period, including both EAV and SAV TRS words, and LOW otherwise.
TRS Based Blanking (H_CONFIG = 1h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.
When DETECT_TRS is HIGH, this pin is ignored at all times.
If DETECT_TRS is set HIGH and TIM_861 is set HIGH, the DETECT_TRS
feature will take priority.
Power supply connection for digital core logic. Connect to +1.2V DC
digital.
Power supply pin for PLL. Connect to +1.2V DC analog.
Loop Filter component connection.
Bandgap voltage filter connection.
These pins are reserved and should be left unconnected.
Input Power
Input
VDD for sensitive analog circuitry. Connect to +3.3VDC analog.
PARALLEL DATA BUS CLOCK.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
3G 20-bit mode
PCLK @ 148.5MHz
3G 10-bit mode DDR
PCLK @ 148.5MHz
HD 20-bit mode
PCLK @ 74.25MHz
HD 10-bit mode
PCLK @ 148.5MHz
SD 20-bit mode
PCLK @ 13.5MHz
SD 10-bit mode
PCLK @ 27MHz
DVB-ASI mode
PCLK @ 27MHz
Input Power GND connection for digital logic. Connect to digital GND.
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
12 of 125

12 Page





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