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PDF A1356 Data sheet ( Hoja de datos )
| Número de pieza | A1356 | |
| Descripción | High Precision Linear Hall-Effect Sensor IC | |
| Fabricantes | Allegro | |
| Logotipo |  |
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A1356
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
Features and Benefits
▪ Simultaneous programming of PWM carrier frequency,
quiescent duty cycle, and sensitivity; for system
optimization
▪ Factory programmed sensitivity temperature coefficient
and quiescent duty cycle drift
▪ Programmability at end-of-line
▪ Pulse width modulated (PWM) output provides increased
noise immunity compared to an analog output
▪ Precise recoverability after temperature cycling
• Output duty cycle clamps provide short circuit diagnostic
capabilities
▪ Optional 50% duty cycle calibration test mode at device
power up
▪ Wide ambient temperature range: –40°C to 150°C
▪ Resistant to mechanical stress
▪ Advanced chopper stabilization circuits and differential
signal path design lead to very low output offset levels
▪ Proprietary on-chip filters provide high output resolution
▪ Wide power supply operating range: 4.5 to 18 V
Package: 3-pin SIP (suffix KB)
Description
The A1356 device is a high precision, programmable open
drain Hall-effect linear sensor IC with a pulse width modulated
(PWM) output. The duty cycle (D) of the PWM output signal
is proportional to an applied magnetic field. The A1356 device
converts an analog signal from its internal Hall element to
a digitally encoded PWM output signal. The coupled noise
immunity of the digitally encoded PWM output is far superior
to the noise immunity of an analog output signal.
The BiCMOS, monolithic circuit inside of theA1356 integrates
a Hall element, precision temperature-compensating circuitry
to reduce the intrinsic sensitivity and offset drift of the Hall
element, a small-signal high-gain amplifier, proprietary
dynamic offset cancellation circuits, and PWM conversion
circuitry. The dynamic offset cancellation circuits reduce
the residual offset voltage of the Hall element. Hall element
offset is normally caused by device overmolding, temperature
dependencies, and thermal stress. The high frequency offset
cancellation (chopping) clock allows for a greater sampling
rate, which increases the accuracy of the output signal and
results in faster signal processing capability.
The A1356 sensor is provided in a lead (Pb) free 3-pin single
inline package (KB suffix), with 100% matte tin leadframe
plating.
Not to scale
VCC/
Programming
Functional Block Diagram
Regulator
PWM Carrier
Generation
PWM
1 Frequency Trim
2
2
1
Chopper
Switches
Amp
Signal
Recovery
Signal
Conditioning
Sensitivity
Trim
Temperature
Compensation
% Duty
Cycle
% Duty Cycle
Temperature
Coefficient
A1356-DS
PWMOUT
GND
1 page  
A1356
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
OPERATING CHARACTERISTICS (continued) Valid over full operating temperature range, TA, VCC = 4.5 to 18 V,
CBYPASS = 0.1 μF, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min. Typ. Max.
Unit
Error Components
Linearity Sensitivity Error2,3
LinERR
–
– ±3.0
%
Symmetry Sensitivity Error2,3
SymERR
–
– ±1.5
%
1After powering on the device, output of device needs time to reach valid magnetic response with a valid PWM output.
2See Characteristic Definitions section.
3Guarenteed by design only. Characterized but not tested in production.
4fC varies up to approximately ± 20% over the full operating ambient temperature range, TA, and process.
5Jitter is dependent on the sensitivity of the device.
6Raw device characteristic values before any programming.
7D(Q)(max) is the value available with all programming fuses blown (maximum programming code set). The D(Q) range is the total range from D(Q)(min)
up to and including D(Q)(max). See Characteristic Definitions section.
8Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
9Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum
specified value of StepD(Q) , StepSENS , or StepfPWM .
10Overall programming value accuracy. See Characteristic Definitions section.
11Programmed at 150°C and calculated relative to 25°C.
12Sensitivity drift from expected value at TA after programming SENSTC. See Characteristic Definitions section.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A1356
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
Typical Application Drawing
V+
CBYPASS
0.1 μF
1
VCC
A1356
PWMOUT
3
GND
2
RPU
CL
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall sen-
sor IC. This makes it difficult to process the signal while main-
taining an accurate, reliable output over the specified operating
temperature and voltage ranges. Chopper stabilization is a unique
approach used to minimize Hall offset on the chip. Allegro
employs a patented technique to remove key sources of the out-
put drift induced by thermal and mechanical stresses. This offset
reduction technique is based on a signal modulation-demodula-
tion process. The undesired offset signal is separated from the
magnetic field-induced signal in the frequency domain, through
modulation. The subsequent demodulation acts as a modulation
process for the offset, causing the magnetic field-induced signal
to recover its original spectrum at base band, while the DC offset
becomes a high-frequency signal. The magnetic-sourced signal
then can pass through a low-pass filter, while the modulated DC
offset is suppressed. In addition to the removal of the thermal and
stress related offset, this novel technique also reduces the amount
of thermal noise in the Hall sensor IC while completely removing
the modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high-frequency sampling
clock. For the demodulation process, a sample-and-hold tech-
nique is used. This high-frequency operation allows a greater
sampling rate, which results in higher accuracy and faster signal-
processing capability. This approach desensitizes the chip to the
effects of thermal and mechanical stresses, and produces devices
that have extremely stable quiescent Hall output voltages and
precise recoverability after temperature cycling. This technique
is made possible through the use of a BiCMOS process, which
allows the use of low-offset, low-noise amplifiers in combination
with high-density logic integration and sample-and-hold circuits.
Regulator
Hall Element
Clock/Logic
Amp
Anti-Aliasing Tuned
LP Filter
Filter
Chopper Stabilization Technique
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet A1356.PDF ] | |
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