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PDF CM1231-02SO Data sheet ( Hoja de datos )
| Número de pieza | CM1231-02SO | |
| Descripción | Low-Capacitance ESD Protection Array | |
| Fabricantes | ON Semiconductor | |
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CM1231-02SO
2, 4 and 8-Channel
Low-Capacitance ESD
Protection Array
Product Description
The CM1231−02SO is specifically designed for next generation
deep submicron ASIC protection. These devices are ideal for
protecting systems with high data and clock rates and for circuits
requiring low capacitive loading such as USB 2.0.
The CM1231−02SO incorporates dual stage ESD architecture
which offers dramatically higher system level ESD protection
compared with traditional single clamp designs. In addition, the
CM1231−02SO provides a controlled filter roll−off for even greater
spurious EMI suppression and signal integrity.
The CM1231−02SO protects against ESD pulses up to ±12 kV
contact on the “OUT” pins per the IEC 61000−4−2 standard.
The device also features easily routed “pass−through” differential
pinouts in a 6−lead SOT23 package.
Features
• Two Channels of ESD Protection
• Exceeds ESD Protection to IEC61000−4−2 Level 4:
• ±12 kV Contact Discharge (OUT Pins)
• Two−Stage Matched Clamp Architecture
• Matching−of−Series Resistor (R) of ±10 mW Typical
• Flow−Through Routing for High−Speed Signal Integrity
• Differential Channel Input Capacitance Matching of 0.02 pF Typical
• Improved Powered ASIC Latchup Protection
• Dramatic Improvement in ESD Protection vs. Best in Class
Single−Stage Diode Arrays
• 40% Reduction in Peak Clamping Voltage
• 40% Reduction in Peak Residual Current
• Withstands over 1000 ESD Strikes*
• Available in a SOT23−6 Package
• These Devices are Pb−Free and are RoHS Compliant
Applications
• USB Devices Data Port Protection
• General High−Speed Data Line ESD Protection
http://onsemi.com
SOT23−6
SO SUFFIX
CASE 527AJ
MARKING DIAGRAM
D312 MG
G
1
D312 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
CM1231−02SO SOT23−6 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*Standard test condition is IEC61000−4−2 level 4 test circuit with each (AOUT/BOUT) pin subjected to ±12 kV contact discharge for 1000 pulses.
Discharges are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run.
© Semiconductor Components Industries, LLC, 2014
January, 2014 − Rev. 4
1
Publication Order Number:
CM1231−02SO/D
1 page  
ESD Strike
CM1231−02SO
I/O Connector
1W
ESD
Protection
Stage 1
ESD
Protection
Stage 2
ASIC
ISHUNT1
ISHUNT2
IRESIDUAL
Figure 2. Dual Clamp ESD Protection Block Diagram
CM1231−02SO ARCHITECTURE OVERVIEW
The two−stage per channel matched clamp architecture
with isolated clamp rails features a series element to
radically reduce the residual ESD current (IRES) that enters
the ASIC under protection (see Figure 3). From stage 1 to
stage 2, the signal lines go through matched dual 1 W
resistors.
The function of the series element (dual 1 W resistors for
the CM1231−02SO) is to optimize the operation of the stage
two diodes to reduce the final IRES current to a minimum
while maintaining an acceptable insertion impedance that is
negligible for the associated signaling levels.
Each stage consists of a traditional low−cap Dual Rail
Clamp structure which steer the positive or negative ESD
current pulse to either the positive (VP) or negative (VN)
supply rail.
A zener diode is embedded between VP and VN, offering
two advantages. First, it protects the VCC rail against ESD
strikes. Second, it eliminates the need for an additional
bypass capacitor to shunt the positive ESD strikes to ground.
The CM1231−02SO therefore replaces as many as seven
discrete components, while taking advantage of precision
internal component matching for improved signal integrity,
which is not otherwise possible with discrete components at
the system level.
VP
Positive Supply Rail
VCC
IESD
1W
IRESIDUAL
Circuitry
Under
Protection
VN Ground Rail
Figure 3. CM1231−02SO Block Diagram (IESD Flow During a Positive Strike)
http://onsemi.com
5
5 Page 
CM1231−02SO
APPLICATION INFORMATION
CM1231−02SO Application and Guidelines
The CM1231−02SO has an integrated zener diode
between VP and VN (for each of the two stages). This greatly
reduces the effect of supply rail inductance L2 on VCL by
clamping VP at the breakdown voltage of the zener diode.
However, for the lowest possible VCL, especially when VP
is biased at a voltage significantly below the zener
breakdown voltage, it is recommended that a 0.22 mF
ceramic chip capacitor be connected between VP and the
ground plane.
With the CM1231−02SO, this additional bypass capacitor
is generally not required.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor
mentioned above should be as close to the VP pin of the
Protection Array as possible, with minimum PCB trace
lengths to the power supply, ground planes and between the
signal input and the ESD device to minimize stray series
inductance.
Figure 14. Typical Layout with Optional VP Cap Footprint
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection,” in the Applications section.
http://onsemi.com
11
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| PDF Descargar | [ Datasheet CM1231-02SO.PDF ] | |
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