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A29400B Schematic ( PDF Datasheet ) - AMIC

Teilenummer A29400B
Beschreibung Boot Sector Flash Memory
Hersteller AMIC
Logo AMIC Logo 




Gesamt 30 Seiten
A29400B Datasheet, Funktion
Preliminary
A29400B Series
512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
June 16, 2016
Remark
Preliminary
PRELIMINARY (June, 2016, Version 0.0)
AMIC Technology, Corp.
AMIC reserves the right to change products and specifications discussed herein without notice.






A29400B Datasheet, Funktion
A29400B Series
Word/Byte Configuration
The BYTE pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE pin is
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by CE and OE .
If the BYTE pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used
as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
selects the device. OE is the output control and gates array
data to the output pins. WE should remain at VIH all the
time during read operation. The internal state machine is set
for reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of
the memory content occurs during the power transition. No
command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, lCC1 in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and
OE to VIH. An erase operation can erase one sector,
multiple sectors, or the entire device. The Sector Address
Tables indicate the address range that each sector
occupies. A "sector address" consists of the address inputs
required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE
input.
The device enters the CMOS standby mode when the CE
& RESET pins are both held at VCC ± 0.5V. (Note that this
is a more restricted voltage range than VIH.) The device
enters the TTL standby mode when CE is held at VIH, while
RESET is held at VCC±0.5V. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the
device is ready to accept another command sequence, to
ensure data integrity.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
PRELIMINARY (June, 2016, Version 0.0)
5
AMIC Technology, Corp.

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A29400B pdf, datenblatt
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
30μs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on
I/O7 - I/O0. The system can use I/O7, or I/O6 and I/O2
together, to determine if a sector is actively erasing or is
erase-suspended. See "Write Operation Status" for
information on these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
A29400B Series
START
Write Erase
Command
Sequence
Data Poll
from System
No
Data = FFh ?
Embedded
Erase
algorithm in
progress
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 3. Erase Operation
PRELIMINARY (June, 2016, Version 0.0)
11
AMIC Technology, Corp.

12 Page





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