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A29010B Schematic ( PDF Datasheet ) - AMIC

Teilenummer A29010B
Beschreibung Uniform Sector Flash Memory
Hersteller AMIC
Logo AMIC Logo 




Gesamt 30 Seiten
A29010B Datasheet, Funktion
A29010B Series
Preliminary
128K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Document Title
128K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
June 16, 2016
Remark
Preliminary
PRELIMINARY (June, 2016, Version 0.0)
AMIC Technology, Corp.
AMIC reserves the right to change products and specifications discussed herein without notice.






A29010B Datasheet, Funktion
A29010B Series
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the
CE and OE pins to VIL. CE is the power control and selects
the device. OE is the output control and gates array data to the
output pins. WE should remain at VIH all the time during read
operation. The internal state machine is set for reading array
data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is necessary
in this mode to obtain array data. Standard microprocessor read
cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to the AC
Read Operations table for timing specifications and to the Read
Operations Timings diagram for the timing waveforms, lCC1 in
the DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and OE
to VIH. An erase operation can erase one sector, multiple
sectors, or the entire device. The Sector Address Tables
indicate the address range that each sector occupies. A "sector
address" consists of the address inputs required to uniquely
select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on I/O7 - I/O0. Standard read cycle
timings apply in this mode. Refer to the "Autoselect Mode" and
"Autoselect Command Sequence" sections for more
information.
ICC2 in the Characteristics table represents the active current
specification for the write mode. The "AC Characteristics"
section contains timing specification tables and timing diagrams
for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 -
I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE input.
The device enters the CMOS standby mode when the CE is
held at VCC ± 0.5V. (Note that this is a more restricted voltage
range than VIH.) The device enters the TTL standby mode when
CE is held at VIH. The device requires the standard access
time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
Sector
SA0
SA1
SA2
SA3
A16
0
0
1
1
Table 2. A29010B Block Sector Address Table
A15 Sector Size (Kbytes)
0 32
1 32
0 32
1 32
Address Range
00000h - 07FFFh
08000h - 0FFFFh
10000h - 17FFFh
18000h - 1FFFFh
PRELIMINARY (June, 2016, Version 0.0)
5
AMIC Technology, Corp.

6 Page









A29010B pdf, datenblatt
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, and I/O7, are provided in the
A29010B to determine the status of a write operation. Table 5
and the following subsections describe the functions of these
status bits. I/O7, I/O6 and I/O2 each offer a method for
determining whether a program or erase operation is complete
or in progress. These three bits are discussed first.
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 2μs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7.This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in a
sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0 on
the following read cycles. This is because I/O7 may change
asynchronously with I/O0 - I/O6 while Output Enable ( OE ) is
asserted low. The Data Polling Timings (During Embedded
Algorithms) figure in the "AC Characteristics" section
illustrates this. Table 5 shows the outputs for Data Polling on
I/O7. Figure 3 shows the Data Polling algorithm.
A29010B Series
START
Read I/O7-I/O0
Address = VA
I/O7 = Data ?
Yes
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
I/O7 = Data ?
Yes
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 3. Data Polling Algorithm
PRELIMINARY (June, 2016, Version 0.0)
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AMIC Technology, Corp.

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