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A290011B Schematic ( PDF Datasheet ) - AMIC

Teilenummer A290011B
Beschreibung Boot Sector Flash Memory
Hersteller AMIC
Logo AMIC Logo 




Gesamt 30 Seiten
A290011B Datasheet, Funktion
Preliminary
A29001B/A290011B Series
128K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
June 16, 2016
Remark
Preliminary
PRELIMINARY (June, 2016, Version 0.0)
AMIC Technology, Corp.
AMIC reserves the right to change products and specifications discussed herein without notice.






A290011B Datasheet, Funktion
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH all
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to
the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing
waveforms, lCC1 in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE and CE
to VIL, and OE to VIH. An erase operation can erase one
sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely select a sector. See the
"Command Definitions" section for details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register
(which is separate from the memory array) on I/O7 - I/O0.
Standard read cycle timings apply in this mode. Refer to
the "Autoselect Mode" and "Autoselect Command
Sequence" sections for more information.
ICC2 in the Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
A29001B/A290011B Series
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
OE input.
The device enters the CMOS standby mode when the CE
& RESET pins ( CE only on A290011B) are both held at
VCC ± 0.5V. (Note that this is a more restricted voltage
range than VIH.) The device enters the TTL standby mode
when CE is held at VIH, while RESET (Not available on
A290011B) is held at VCC±0.5V. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the
standby current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin (N/A on A290011B)
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
The RESET pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
PRELIMINARY (June, 2016, Version 0.0)
5
AMIC Technology, Corp.

6 Page









A290011B pdf, datenblatt
A29001B/A290011B Series
Table 5. A29001B/A290011B Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2 - 4)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Notes 5, 6)
1 RA RD
Reset (Note 6)
1 XXX F0
Manufacturer ID
Top
Device ID
Autoselect
Bottom
(Note 7) Continuation ID
4 555 AA
4 555 AA
4 555 AA
2AA 55
2AA 55
2AA 55
555
555
555
90 X00 37
A1
90 X01
4C
90 X03 7F
Program
Sector Protect Verify
4 555 AA
(Note 8)
4 555 AA
2AA 55
2AA 55
555
555
SA 00
90
X02 01
A0 PA PD
Chip Erase
6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase
6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9)
1 XXX B0
Erase Resume (Note 10)
1 XXX 30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A16 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend
mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
11. The time between each command cycle has to be less than 50μs.
PRELIMINARY (June, 2016, Version 0.0)
11
AMIC Technology, Corp.

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