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A25LQ64 Schematic ( PDF Datasheet ) - AMIC

Teilenummer A25LQ64
Beschreibung 64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO
Hersteller AMIC
Logo AMIC Logo 




Gesamt 30 Seiten
A25LQ64 Datasheet, Funktion
A25LQ64 Series
64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO
(SERIAL MULTI I/O) FLASH MEMORY
Document Title
64M-BIT (x1 / x2 / x4) 3 . 3 V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
1.0
1.1
1.2
1.3
1.4
History
Initial issue
Add 16-pin SOP (300mil) package type
Add 8-pin SOP (209mil) package type
Add FAST READ DUAL OUTPUT (3Bh) command
Refine QE bit definition to control only hardware protect function
Change Figure-36-1, 36-2 and refine erase cycling
Final version release
SFDP address 08h ID code 37 changed to 00
SFDP address 38h & 4Ah EB dummy code data bits 04~00 changed
from 00110b to 00100b
Add A25LQ64M-FE type in ordering information
This type fixes QE bit “1”
The hardware protect function is disabled in this type
Add 8-pin DIP package type
Modify the fast program time spec.
Change Figure 7. unique ID to 64 bytes
Issue Date
June 2, 2012
June 28, 2012
July 10, 2012
November 1, 2012
November 19, 2012
January 14, 2013
March 5, 2013
May 9, 2013
July 01, 2013
January 9, 2014
July 3, 2014
Remark
Preliminary
Final
(July, 2014, Version 1.4)
AMIC Technology Corp.






A25LQ64 Datasheet, Funktion
A25LQ64 Series
DATA PROTECTION
The A25LQ64 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transition.
During power up the device automatically resets the state
machine in the Read mode. In addition, with its control register
architecture, alteration of the memory contents only occurs
after successful completion of specific command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up and
power-down transition or system noise.
„ Power-on reset and tPUW: to avoid sudden power switch
by system power supply transition, the power-on reset
and tPUW (internal timer) may protect the Flash.
„ Valid command length checking: The command length
will be checked whether it is at byte base and completed
on byte boundary.
„ Write Enable (WREN) command: WREN command is
required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to
reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase 32KB (BE32K) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
- Program/Erase Suspend
- Softreset command completion
- Write Security Register (WRSCUR) command completion
„ Deep Power Down Mode: By entering deep power down
mode, the flash device also is under protected from
writing all commands except Release from deep power
down mode command (RDP) and Read Electronic
Signature command (RES) and softreset command.
„ Block lock protection and additional 4K-bit secured OTP:
there are block protection and 4K secured OTP which
protect content from inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1,
BP0) bits to allow part of memory to be protected as read
only. The protected area definition is shown as table of
"Protected Area Sizes", the protected areas are more
flexible which may protect various area by setting value of
BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Protected Mode (HPM) use W (IO2) to
protect the (BP3, BP2, BP1, BP0) bits and Status Register
Write Protect bit. When using A25LQ64M-FE, the Hardware
Protected Mode (HPM) is disabled.
- In four I/O and QPI mode, the feature of HPM will be disabled
(July, 2014, Version 1.4)
5 AMIC Technology Corp.

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A25LQ64 pdf, datenblatt
Reset QPI mode (RSTQIO)
By issuing F5H command, the device is reset to 1-I/O SPI mode.
Figure 5. Reset QPI Mode (Command F5H)
S
C
IO[3:0]
F5
A25LQ64 Series
Fast QPI Read mode (FASTRDQ)
To increase the code transmission speed, the device
provides a "Fast QPI Read Mode" (FASTRDQ). By issuing
command code EBH, the FASTRDQ mode is enable. The
number of dummy cycle increase from 4 to 6 cycles. The
read cycle frequency will increase from 84MHz to 104MHz.
Figure 6. Fast QPI Read Mode (FASTRDQ) (Command EBH)
S
MODE 3
C
MODE 0
01
23 4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
MODE 3
MODE 0
IO[3:0]
EB A5 A4 A3 A2 A1 A0 X X X X X X H0 L0 H1 L1 H2 L2 H3 L3
Data In
MSB
Data Out
(July, 2014, Version 1.4)
11 AMIC Technology Corp.

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