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A25LQ16 Schematic ( PDF Datasheet ) - AMIC

Teilenummer A25LQ16
Beschreibung Dual/Quad-I/O Serial Flash Memory
Hersteller AMIC
Logo AMIC Logo 




Gesamt 30 Seiten
A25LQ16 Datasheet, Funktion
A25LQ16 Series
16Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory
with 100MHz Uniform 4KB Sectors
Document Title
16Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory with 100MHz Uniform
4KB Sectors
Revision History
Rev. No.
0.0
1.0
1.1
1.2
History
Initial issue
Final version release
Change tSE(typ.) from 150ms to 0.08s
Change tSE(max.) from 280ms to 0.2s
Change tBE(typ,) from 0.7s to 0.5s
P50: Change ICC6 & ICC7(max.) from 15mA to 25mA
Issue Date
August 17, 2011
August 29, 2011
November 15, 2011
Remark
Preliminary
Final
March 29, 2012
(March, 2012, Version 1.2)
AMIC Technology Corp.






A25LQ16 Datasheet, Funktion
SPI OPERATIONS
Standard SPI Instructions
The A25LQ16 is accessed through an SPI compatible bus
consisting of four signals: Serial Clock (C), Chip Select ( S ),
Serial Data Input (DI), and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write
instructions, addresses or data to the device on the rising
edge of Serial Clock (C). The DO output pin is used to read
data or status from the device on the falling edge of Serial
Clock (C).
Dual SPI Instructions
The A25LQ16 supports Dual SPI operation when using the
“FAST_READ_DUAL_OUTPUT and FAST_READ_DUAL_
INPUT_OUTPUT” (3B and BB hex) instructions. These
instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices.
The Dual Read instructions are ideal for quickly downloading
code to RAM upon power-up (code-shadowing) or for
executing non-speed-critical code directly from the SPI bus
(XIP). When using Dual SPI instructions the DI and DO pins
become bidirectional I/O pins; IO0 and IO1.
Quad SPI Instructions
The A25LQ16 supports Quad SPI operation when using the
“FAST_READ_QUAD_OUTPUT” (6B hex) and
“FAST_READ_QUAD_INPUT_OUTPUT” (EB hex)
instructions. This instruction allows data to be transferred to
or from the device four to six times the rate of ordinary Serial
Flash. These 2 instructions offer a significant improvement in
continuous and random access transfer rates allowing fast
code-shadowing to RAM or execution directly from the SPI
bus (XIP). When using Quad SPI instructions the DI and DO
pins become bi-directional IO0 and IO1, and the W and
HOLD pins become IO2 and IO3 respectively. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in
Status Register-2 to be set.
A25LQ16 Series
Hold Condition
The Hold ( HOLD ) signal is used to pause any serial
communications with the device without resetting the clocking
sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress. The HOLD function is only
available for standard SPI and Dual SPI operation, not during
Quad SPI.
To enter the Hold condition, the device must be selected, with
Chip Select ( S ) Low.
The Hold condition starts on the falling edge of the Hold
(HOLD ) signal, provided that this coincides with Serial Clock
(C) being Low (as shown in Figure 2.).
The Hold condition ends on the rising edge of the Hold
(HOLD ) signal, provided that this coincides with Serial Clock
(C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after
Serial Clock (C) next goes Low. This is shown in Figure 2.
During the Hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DI) and Serial Clock (C)
are Don’t Care.
Normally, the device is kept selected, with Chip Select ( S )
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
If Chip Select ( S ) goes High while the device is in the Hold
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
necessary to drive Hold ( HOLD ) High, and then to drive Chip
Select ( S ) Low. This prevents the device from going back to
the Hold condition.
Figure 2. Hold Condition Activation
C
HOLD
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
(March, 2012, Version 1.2)
5 AMIC Technology Corp.

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A25LQ16 pdf, datenblatt
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input(s) IO0 (IO1, IO2, IO3) is (are) sampled on the
first rising edge of Serial Clock (C) after Chip Select ( S ) is
driven Low. Then, the one-byte instruction code must be
shifted in to the device, most significant bit first, on Serial Data
Input(s) IO0 (IO1, IO2, IO3), each bit being latched on the rising
edges of Serial Clock (C).
The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by dummy bytes (don’t
care), or by a combination or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Data Bytes at Higher Speed
by Dual Output (FAST_READ_DUAL_OUTPUT), Read Data
Bytes at Higher Speed by Dual Input and Dual Output
(FAST_READ_DUAL_INPUT_OUTPUT) , Read Data Bytes at
Higher Speed by Quad Output (FAST_READ_QUAD
_OUTPUT), Read Data Bytes at Higher Speed by Quad Input
and Quad Output (FAST_READ_QUAD_INPUT_OUTPUT),
Read OTP (ROTP), Read Identification (RDID), Read
Electronic Manufacturer and Device Identification (REMS),
A25LQ16 Series
Read Status Register (RDSR) or Release from Deep
Power-down, Read Device Identification and Read Electronic
Signature (RES) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip Select ( S )
can be driven High after any bit of the data-out sequence is
being shifted out.
In the case of a Page Program (PP), Program OTP (POTP),
Dual Input Fast Program (DIFP), Quad Input Fast Program
(QIFP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR), Write Enable (WREN), Write
Disable (WRDI) or Deep Power-down (DP) instruction, Chip
Select ( S ) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That
is, Chip Select ( S ) must driven High when the number of
clock pulses after Chip Select ( S ) being driven Low is an
exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
(March, 2012, Version 1.2)
11 AMIC Technology Corp.

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