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CH7008A-V Schematic ( PDF Datasheet ) - ETC

Teilenummer CH7008A-V
Beschreibung Digital PC to TV Encoder Features
Hersteller ETC
Logo ETC Logo 




Gesamt 49 Seiten
CH7008A-V Datasheet, Funktion
CHRONTEL
CH7008A
Digital PC to TV Encoder Features
Features
• Support for low voltage interface to VGA controller
• Universal digital interface accepts YCrCb (CCIR656)
or RGB (15, 16 or 24-bit multiplexed) video data in
both non-interlaced and interlaced formats
• TrueScale TM rendering engine supports underscan
operations for various graphic resolutions† ¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering
• Enhanced dot crawl control and area reduction
• Fully programmable through I2C port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin PLCC, 44-pin TQFP
General Description
Chrontel’s CH7008 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output on non-DVD enabled systems.
Suggested application use with the Intel 810 chipset &
Intel 810E chipset.* It provides a universal digital input
port to accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format.
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its TrueScaleTM
scaling and deflickering engine, the CH7008 supports full
vertical and horizontal underscan capability and operates
in 5 different resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7008 ideal for system-level
PC solutions. All features are software programmable
through a standard I2C port, to enable a complete PC
solution using a TV as the primary display.
Patent number 5,781,241
¥ Patent number 5,914,753
LINE
MEMORY
D[11:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
YUV-RGB CONVERTER
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
GPIO[1:0]
I2C REGISTER &
CONTROL BLOCK
SYSTEM CLOCK
PLL
TIMING & SYNC
GENERATOR
SC SD
RESET*
XCLK*
H V XI/FIN XO CSYNC P-OUT DS/BCO
Figure 1: Functional Block Diagram
201-0000-027 Rev 2.2, 9/30/99 *Intel 810 and Intel 810E are Trademarks of Intel Corp
Y/R
C/G
CVBS/B
ISET
1






CH7008A-V Datasheet, Funktion
CHRONTEL
CH7008A
Digital Video Interface
The CH7008 digital video interface provides a flexible digital interface between a computer graphics
controller and the TV encoder IC forming the ideal quality/cost configuration for performing the TV-output
function. This digital interface consists of up to 12 data signals and 4 control signals, all of which are
subject to programmable control through the CH7008 register set. This interface can be configured as 8
or 12-bit inputs operating in multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit
color depth) data formats and will accept both non-interlaced and interlaced data formats. A summary of
the input data format modes is as follows:
Table 2. Input Data Formats
Bus
Width
8-bit
8-bit
8-bit
12-bit
12-bit
Transfer Mode
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
Color Space and Depth
RGB 15-bit
RGB 16-bit
YCrCb (24-bit)
RGB 24
RGB 24
Format Reference
5-5-5 over two bytes
5-6-5 over two bytes
Cb,Y0,Cr,Y1,(CCIR656 style)
8-8-8 over two words - ‘C’ version
8-8-8 over two words - ‘I’ version
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7008 can operate in either master (the CH7008 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or
3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7008 will
automatically use both clock edges, if a multiplexed data format is selected.
Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7008. In the case of CCIR656 style input (IDF = 9), embedded sync may also be
used. In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first
value of the (Total Pixels/line x Total Lines/Frame) column of Table 13 on page 29 (Display Mode Register 00H
description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync
signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of Table 13
on page 29.
Master Clock Mode: The CH7008 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal
will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel
data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits
back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the
specified setup and hold times with respect to the pixel clock.
Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after the
leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus
horizontal sync width, will determine when the chip will begin to sample pixels.
6 201-0000-027 Rev 2.2, 9/30/99

6 Page









CH7008A-V pdf, datenblatt
CHRONTEL
CH7008A
Display Modes (continued)
additional filtering for enhancing the readability of text. These modes are fully programmable via I2C under the
flicker filter register.
Internal Voltage Reference
An on chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a
reference resistor at pin ISET, and register controlled divider, sets the output ranges of the DACs. The CH7008
bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal for PAL or NTSC-J,
which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor from ISET
to ground is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for
DAC output is 1/48th. Therefore, for each DAC, the current output per LSB step is determined by the following
equation:
ILSB = V(ISET)/ISET reference resistor * 1/GAIN
For DACG=0, this is: ILSB = 1.235/360 * 1/48 = 71.4 µA (nominal)
For DACG=1, this is: ILSB = 1.317/360 * 1/48 = 76.2 µA (nominal)
Power Management
The CH7008 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off
and Composite Off to provide optimal power consumption for the application involved. Using the programmable
power down modes accessed over the I2C port, the CH7008 may be placed in either Normal state, or any of the four
power managed states, as listed below (see “Power Management Register” under the Register Descriptions section
for programming information). To support power management, a TV sensing function (see “Connection Detect
Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to either
S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if
TV is sensed only on composite, the S-Video Off mode could be set by software).
Table 8. Power Management
Operating State
Normal (On):
Power Down:
S-Video Off:
Composite Off:
Full Power Down:
Functional Description
In the normal operating state, all functions and pins are active.
In the power-down state, most pins and circuitry are disabled.The DS/BCO pin
will continue to provide either the VCO divided by K3, or 14.318 MHz out when
selected as an output, and the P-OUT pin will continue to output a clock
reference when in master clock mode.
Power is shut off to the unused DACs associated with S-Video outputs.
In Composite-off state, power is shut off to the unused DAC associated with
CVBS output.
In this power-down state, all but the I2C circuits are disabled. This places the
CH7008 in its lowest power consumption mode.
Luminance and Chrominance Filter Options
The CH7008 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S-
Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown,
the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and
chrominance video bandwidth output is shown in Table 9.
12 201-0000-027 Rev 2.2, 9/30/99

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