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CGS74C2526 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CGS74C2526
Beschreibung 1-to-8 Minimum Skew Clock Driver
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 10 Seiten
CGS74C2526 Datasheet, Funktion
September 1995
CGS74C2525  CGS74CT2525
CGS74C2526  CGS74CT2526
1-to-8 Minimum Skew Clock Driver
The CGS ’C CT2525 is a minimum skew clock driver with
one input driving eight outputs specifically designed for sig-
nal generation and clock distribution applications The ’2525
is designed to distribute a single clock to eight separate
receivers with low skew across all outputs during both the
tPLH and tPHL transitions The ’2526 is similar to the ’2525
but contains a multiplexed clock input to allow for systems
with dual clock speeds or systems where a separate test
clock has been implemented
Features
Y These CGS devices implement National’s FACTTM
family
Y Ideal for signal generation and clock distribution
Y Guaranteed pin to pin and part to part skew
Y Multiplexed clock input (’2526)
Y Guaranteed 2 kV minimum ESD protection
Y Symmetric output current drive of 24 mA for IOL IOH
Y ’CT has TTL-compatible inputs
Y These products are identical to 74AC ACT2525 and
2526
Y Available as Mil Aero versions
54AC ACT2525
54AC ACT2526
Logic Symbols
’2525
Connection Diagrams
Pin Assignment
for DIP and SOIC
’2525
’2526
TL F 10684 – 1
TL F 10684 – 2
’2526
TL F 10684 – 3
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACTTM is a trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 10684
RRD-B30M106 Printed in U S A
TL F 10684 – 4
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CGS74C2526 Datasheet, Funktion
AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise (Continued)
Symbol
Parameter
VCC
Range
(V)
(Note 6)
CGS74CT
TA e a25 C
CL e 50 pF
Min Typ Max
54ACT
TA e b55 C
to a125 C
CL e 50 pF
Min Max
CGS74CT
TA e b40 C
to a85 C
CL e 50 pF
Min Typ Max
Units
tPLH
tPHL
tOSHL
Propagation Delay
SEL to On (’2526)
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
5 0 5 1 8 5 12 4
50 02
4 4 14 1 ns
550 ps
tOSLH
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
50
02
550 ps
tOST
Maximum Skew
Opposite Edge
Output-to-Output (Note 7)
Variation
50
04
1 0 ns
tPV Maximum Skew AC2525
Part-to-Part
ACT2525
Variation (Note 8) AC2526
50
35
ns
ACT2526 5 0
50
ns
trise Maximum
tfall Rise Fall Time
(20% to 80% VCC)
trise Maximum
tfall Rise Fall Time
(0 8V 2 0V and 2 0V 0 8V)
50
30
09
3 75 ns
1 1 ns
Note 2 All outputs loaded thresholds on input associated with output under test
Note 3 IIN and ICC 3 0V are guaranteed to be less than or equal to the respective limit
ICC for 54AC 25 C is identical to CGS74C 25 C
Note 4 Maximum test duration 2 0 ms one output loaded at a time
5 5V VCC
Note 5 ICC for 54ACT 25 C is identical to CGS74CT 25 C
Note 6 Voltage Range 5 0 is 5 0V g0 5V voltage range 3 3 is 3 3V g0 3V
Note 7 Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) or in opposite directions both
HL and LH (tOST) tOSHL and tOSLH are characterized and guaranteed by design 1 MHz
Note 8 Part-to-part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device The parameter is
specified for a given set of conditions (i e capacitive load VCC temperature of outputs switching etc ) Parameter guaranteed by design
Note 9 Load capacitance includes the test jig
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