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PDF PCF85063TP Data sheet ( Hoja de datos )

Número de pieza PCF85063TP
Descripción Tiny Real-Time Clock/calendar
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCF85063TP Hoja de datos, Descripción, Manual

PCF85063TP
Tiny Real-Time Clock/calendar
Rev. 4 — 6 May 2015
Product data sheet
1. General description
The PCF85063TP is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low
power consumption. An offset register allows fine-tuning of the clock. All addresses and
data are transferred serially via the two-line bidirectional I2C-bus. Maximum bus speed is
400 kbit/s. The register address is incremented automatically after each written or read
data byte.
For a selection of NXP Real-Time Clocks, see Table 35 on page 43
2. Features and benefits
Provides year, month, day, weekday, hours, minutes, and seconds based on a
32.768 kHz quartz crystal
Clock operating voltage: 0.9 V to 5.5 V
Low current: typical 0.22 A at VDD = 3.3 V and Tamb = 25 C
400 kHz two-line I2C-bus interface (at VDD = 1.8 V to 5.5 V)
Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz,
8.192 kHz, 4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz)
Selectable integrated oscillator load capacitors for CL = 7 pF or CL = 12.5 pF
Minute and half minute interrupt
Oscillator stop detection function
Internal Power-On Reset (POR)
Programmable offset register for frequency adjustment
3. Applications
Digital still camera
Digital video camera
Printers
Copy machines
Mobile equipment
Battery powered devices
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

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PCF85063TP pdf
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8.1 Registers organization
Table 5. Registers overview
Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 8 on page 10.
Address Register name Bit
7654321
Control and status registers
00h Control_1
EXT_TEST -
STOP
SR
-
CIE 12_24
01h Control_2
-
-
MI HMI TF COF[2:0]
02h Offset
MODE
OFFSET[6:0]
03h RAM_byte
B[7:0]
Time and date registers
04h Seconds
OS
SECONDS (0 to 59)
05h Minutes
-
MINUTES (0 to 59)
06h Hours
-
-
AMPM HOURS (1 to 12) in 12 hour mode
HOURS (0 to 23) in 24 hour mode
07h Days - - DAYS (1 to 31)
08h Weekdays
-
-
-
-
-
WEEKDAYS (0 to 6)
09h Months
-
-
-
MONTHS (1 to 12)
0Ah Years
YEARS (0 to 99)
Reference
0
CAP_SEL
Section 8.2.1
Section 8.2.2
Section 8.2.3
Section 8.2.4
Section 8.3.1
Section 8.3.2
Section 8.3.3
Section 8.3.4
Section 8.3.5
Section 8.3.6
Section 8.3.7

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PCF85063TP arduino
NXP Semiconductors
PCF85063TP
Tiny Real-Time Clock/calendar
8.2.2 Register Control_2
Table 9. Control_2 - control and status register 2 (address 01h) bit description
Bit Symbol
Value
Description
7 to 6 -
00 unused
5 MI
minute interrupt
0[1] disabled
1 enabled
4 HMI
half minute interrupt
0[1] disabled
1 enabled
3 TF
timer flag
0[1] no timer interrupt generated
1 flag set when timer interrupt generated
2 to 0 COF[2:0]
see Table 11 CLKOUT control
[1] Default value.
8.2.2.1 MI and HMI: minute and half minute interrupt
The minute interrupt (bit MI) and half minute interrupt (bit HMI) are pre-defined timers for
generating interrupt pulses on pin INT; see Figure 7. The timers are running in sync with
the seconds counter (see Table 19 on page 17).
The minute and half minute interrupts must only be used when the frequency offset is set
to normal mode (MODE = 0), see Section 8.2.3. In normal mode, the interrupt pulses on
pin INT are 164 s wide.
When starting MI, the first interrupt will be generated after 1 second to 59 seconds. When
starting HMI, the first interrupt will be generated after 1 second to 29 seconds.
Subsequent periods do not have such a delay. The timers can be enabled independently
from one another. However, a minute interrupt enabled on top of a half minute interrupt is
not distinguishable.
VHFRQGVFRXQWHU  
 
PLQXWHVFRXQWHU
 
,17ZKHQ0,HQDEOHG
7)ZKHQ0,HQDEOHG
In this example, the TF flag is not cleared after an interrupt.
Fig 7. INT example for MI
 
DDD
PCF85063TP
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 May 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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