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CGS2536TV Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CGS2536TV
Beschreibung Commercial/ Industrial Quad 1 to 4 Clock Drivers
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 8 Seiten
CGS2536TV Datasheet, Funktion
September 1995
CGS2536V
Commercial Quad 1 to 4 Clock Drivers
CGS2536TV
Industrial Quad 1 to 4 Clock Drivers
General Description
These Clock Generation and Support clock drivers are spe-
cifically designed for driving memory arrays requiring large
fanouts while operating at high speeds
This device meets the rise and fall time requirements of the
90 MHz and 100 MHz PentiumTM procrssors
The CGS2536 I O structures are CMOS The outputs are
separated into two banks of eight One bank consists of
divide by two outputs the other straight-through buffers
Within each bank half the outputs are inverting the other
half non-inverting
The CGS2536 specification guarantees part-to-part skew
variation
Features
Y Guaranteed
1 0 ns rise and fall times while driving 12 inches of
50X microstrip terminated with 25 pF
350 ps pin-to-pin skew (tOSLH and tOSHL)
Y 650 ps part-to-part variation on positive or negative
transition
Y Operates with either 3 3V or 5 0V supply
Y Inputs 5V tolerant with VCC in 3 3V range
Y Symmetric output current drive 24 mA IOH IOL
Y Industrial temperature of b40 C to a85 C
Y Symmetric package orientation
Y Large fanout for memory driving applications
Y Guaranteed 2 kV ESD protection
Y Implemented on National’s ABT family process
Y 28-pin PLCC for optimum skew performance
Connection Diagrams
Pin Assignment for 28-Pin PLCC
Truth Table
Input
In 0
In 1
In 2
In 3
Output
ABCD Out (0) d 2
ABCD Out (1) d 2
ABCD Out (2)
ABCD Out (3)
PentiumTM is a trademark of Intel Corporation
C1995 National Semiconductor Corporation TL F 12325
TL F 12325 – 1
CGS2536
TL F 12325 – 2
RRD-B30M105 Printed in U S A






CGS2536TV Datasheet, Funktion
CGS2534 35 36 37
Memory Array Driving
In order to minimize the total load on the address bus quite
often memory arrays are driven by buffers while having the
inputs of the buffers tied together Although this practice
was feasible in the conventional memory designs in today’s
high speed large buswidth designs which require address
fetching at higher speeds this technique produces many
undesired results such as cross-talk and over undershoot
CGS2534 35 36 37 Quad 1 to 4 clock drivers were de-
signed specifically to address these application issues on
high speed large memory arrays systems
These drivers are optimized to drive large loads with 3 5 ns
propagation delays These drivers produce less noise while
reducing the total capacitive loading on the address bus by
having only four inputs tied together (see the diagram be-
low point A) This helps to minimize the overshoot and un-
dershoot by having only four outputs being switched simul-
taneously
Also this larger fan-out helps to save board space since for
every one of these drivers two conventional buffers were
typically being used
Another feature associated with these clock drivers is a
350 ps pin-to-pin skew specification The minimum skew
specification allows high speed memory system designers
to optimize the performance of their memory sub-system by
operating at higher frequencies without having concerns
about output-to-output (bank-to-bank) synchronization prob-
lem which are associated with driving high capacitive loads
(Point B)
The diagram below depicts a ‘‘2534 35 36 37’’ a memory
subsystem operating at high speed with large memory ca-
pacity The address bus is common to both the memory and
the CPU and I Os
These drivers can operate beyond 125 MHz and are also
available in 3V – 5V TTL CMOS versions with large current
drive
Device
2534
2535
2536
2537
VCC
5
3 or 5
3 or 5
5
IO
TTL
CMOS
CMOS
TTL
Output Configuration
Inverting quad 1–4
Non-inverting quad 1–4
Inverting Non-inverting d2
Inverting quad 1–4 with series 8X output resistors
6
TL F 12325 – 7

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