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PDF CGS2535TV Data sheet ( Hoja de datos )
| Número de pieza | CGS2535TV | |
| Descripción | Commercial Quad 1 to 4 Clock Drivers/Industrial Quad 1 to 4 Clock Drivers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 1997
CGS2535V/CGS2535TV
Commercial Quad 1 to 4 Clock Drivers/Industrial Quad
1 to 4 Clock Drivers
General Description
These Clock Generation and Support clock drivers are spe-
cifically designed for driving memory arrays requiring large
fanouts while operating at high speeds.
This device meets the rise and fall time requirements of the
90 and 100 MHz Pentium™ processors.
The CGS2535 is a non-inverting 4 to 16 driver with CMOS
I/O structures. The CGS2535 specification guarantees
part-to-part skew variation.
Features
n Guaranteed:
— 1.0 ns rise and fall times while driving 12 inches of
50Ω microstrip terminated with 25 pF
— 350 ps pin-to-pin skew (tOSLH and tOSHL)
n 650 ps part-to-part variation on positive or negative
transition @ 5V VCC
n Operates with either 3.3V or 5.0V supply
n Inputs 5V tolerant with VCC in 3.3V range
n Symmetric output current drive: 24 mA IOH/IOL
n Industrial temperature range −40˚C to +85˚C
n Symmetric package orientation
n Large fanout for memory driving applications
n Guaranteed 2 kV ESD protection
n Implemented on National’s ABT family process
n 28-pin PLCC for optimum skew performance
Connection Diagrams
Pin Assignment for 28-Pin PLCC
CGS2535
Truth Table
Input
In (0–3)
Output
ABCD Out (0–3)
DS011954-5
DS011954-2
Pentium™ is a trademark of Intel Corporation.
© 1997 National Semiconductor Corporation DS011954
http:\\www.national.com
1 page  
CGS2534/35/36/37
Memory Array Driving
In order to minimize the total load on the address bus, quite
often memory arrays are driven by buffers while having the
inputs of the buffers tied together. Although this practice was
feasible in the conventional memory designs, in today’s high
speed, large buswidth designs which require address fetch-
ing at higher speeds, this technique produces many undes-
ired results such as cross-talk and over/undershoot.
CGS2534/35/36/37 Quad 1 to 4 clock drivers were designed
specifically to address these application issues on high
speed, large memory arrays systems.
These drivers are optimized to drive large loads, with 3.5 ns
propagation delays. These drivers produce less noise while
reducing the total capacitive loading on the address bus by
having only four inputs tied together (see the diagram below,
point A). This helps to minimize the overshoot and under-
shoot by having only four outputs being switched simulta-
neously.
Also this larger fan-out helps to save board space since for
every one of these drivers, two conventional buffers were
typically being used.
Another feature associated with these clock drivers is a
350 ps pin-to-pin skew specification. The minimum skew
specification allows high speed memory system designers to
optimize the performance of their memory sub-system by
operating at higher frequencies without having concerns
about output-to-output (bank-to-bank) synchronization prob-
lems which are associated with driving high capacitive loads
(Point B).
The diagram below depicts a “2534/35/36/37” a memory
subsystem operating at high speed with large memory ca-
pacity. The address bus is common to both the memory and
the CPU and I/Os.
These drivers can operate beyond 125 MHz, and are also
available in 3V–5V TTL/CMOS versions with large current
drive .
Device
2534
2535
2536
2537
VCC
5
3 or 5
3 or 5
5
I/O
TTL
CMOS
CMOS
TTL
DS011954-8
Output Configuration
Inverting quad 1–4
Non-inverting quad 1–4
Inverting, Non-inverting, ÷2
Inverting quad 1–4 with series 8Ω output resistors
5 http:\\www.national.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CGS2535TV.PDF ] | |
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