Datenblatt-pdf.com


GT24C512 Schematic ( PDF Datasheet ) - Giantec Semiconductor

Teilenummer GT24C512
Beschreibung 2-WIRE 512K Bits Serial EEPROM
Hersteller Giantec Semiconductor
Logo Giantec Semiconductor Logo 




Gesamt 20 Seiten
GT24C512 Datasheet, Funktion
GT24C512
GT24C512
2-WIRE
512K Bits
Serial EEPROM
Copyright © 2013 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without
notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance
and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers
are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
Giantec Semiconductor, Inc.
vo
www.giantec-semi.com
1/20






GT24C512 Datasheet, Funktion
GT24C512
5. Device Operation
The GT24C512 serial interface supports communications
using industrial standard 2-wire bus protocol, such as I2C.
5.1 2-WIRE Bus
The two-wire bus is defined as Serial Data (SDA), and
Serial Clock (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Start and Stop conditions. The
GT24C512 is the Slave device.
5.2 The Bus Protocol
Data transfer may be initiated only when the bus is not
busy.
During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA line
while the SCL line is high will be interpreted as a Start or
Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated by
a Stop condition.
5.3 Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when SCL
is High. The EEPROM monitors the SDA and SCL lines and
will not respond until the Start condition is met.
5.4 Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
5.5 Acknowledge
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
5.6 Reset
The GT24C512 contains a reset function in case the 2-wire
bus transmission on is accidentally interrupted (e.g. a
power loss), or needs to be terminated mid-stream. The
reset is initiated when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up to
nine times. (For each clock signal transition to High, the
Master checks for a High level on SDA.)
5.7 Standby Mode
While in standby mode, the power consumption is minimal.
The GT24C512 enters into standby mode during one of the
following conditions: a) After Power-up, while no Op-code is
sent; b) After the completion of an operation and followed
by the Stop signal, provided that the previous operation is
not Write related; or c) After the completion of any internal
write operations.
5.8 Device Addressing
The Master begins a transmission on by sending a Start
condition, then sends the address of the particular Slave
devices to be communicated. The Slave device address is 8
bits format as shown in Figure. 5-5.
The four most significant bits of the Slave address are fixed
(1010) for GT24C512.
The next three bits, A0, A1 and A2, of the Slave address are
specifically related to EEPROM. Up to eight GT24C512
units can be connected to the 2-wire bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, Read operation is selected. While it is set to 0, Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte appropriately, the associated 2-wire Slave
device, GT24C512, will respond with ACK on the SDA line.
Then GT24C512 will pull down the SDA on the ninth clock
cycle, signaling that it received the eight bits of data.
The GT24C512 then prepares for a Read or Write operation
by monitoring the bus.
Giantec Semiconductor, Inc.
v0
www.giantec-semi.com
6/20

6 Page









GT24C512 pdf, datenblatt
GT24C512
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS Supply Voltage
-0.5 to + 6.5
V
VP Voltage on Any Pin
–0.5 to VCC + 0.5
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT Output Current
5 mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6.2 Operating Range
Range
Industrial
Ambient Temperature (TA)
–40°C to +85°C
Note: Giantec offers Industrial grade for Commercial applications (0°C to +70°C).
VCC
1.7V to 5.5V
6.3 Capacitance
Symbol
Parameter[1, 2]
Conditions
Max.
CIN Input Capacitance VIN = 0V
6
CI/O Input / Output Capacitance VI/O = 0V
8
Notes: [1] Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
[2] Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
Unit
pF
pF
Giantec Semiconductor, Inc.
v0
www.giantec-semi.com
12/20

12 Page





SeitenGesamt 20 Seiten
PDF Download[ GT24C512 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GT24C5122-WIRE 512K Bits Serial EEPROMGiantec Semiconductor
Giantec Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche