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Número de pieza | EN27LN1G08 | |
Descripción | 3.3V NAND Flash Memory | |
Fabricantes | EON | |
Logotipo | ||
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1 Gigabit (128 M x 8), 3.3 V NAND Flash Memory
EN27LN1G08
Features
• Voltage Supply: 2.7V ~ 3.6V
• Organization
- Memory Cell Array :
(128M + 4M) x 8bit for 1Gb
- Data Register : (2K + 64) x 8bit
• Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
• Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 25ns (Min.)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
- Page Program Time : 200µs (Typ.)
- Block Erase Time : 1.5ms (Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
• Reliable CMOS Floating-Gate Technology
• Endurance:
- 100K Program/Erase Cycles (with 1 bit/528 bytes
ECC)
- Data Retention: 10 Years
• Command Driven Operation
• Cache Program Operation for High Performance
Program
• Copy-Back Operation
• OTP Operation
• Unique ID for Copyright Protection
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03
1 page Block Diagram
Functional Block Diagram
EN27LN1G08
Array Organization
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03
5 Page EN27LN1G08
Program / Erase Characteristics
Parameter
Program Time
Dummy Busy Time for Cache
Program
Symbol
tPROG(1)
tCBSY(2)
Min.
-
-
Typ.
200
3
Max.
700
700
Unit
us
us
Number of Partial Program Cycles
in the Same Page
NOP
-
-
4 Cycle
Block Erase Time
tBERS
-
1.5 10 ms
Note:
1. Typical program time is defined as the time within which more than 50% of the whole pages are
programmed at 3.3V VCC and 25°C temperature.
2. Max. time of tCBSY depends on timing between internal program completion and data in.
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min.
Max.
Unit
CLE Setup Time
tCLS(1)
12
- ns
CLE Hold Time
tCLH
5
- ns
CE# Setup Time
tCS 20
- ns
CE# Hold Time
tCH 5
- ns
WE# Pulse Width
ALE Setup Time
tWP
tALS(1)
12
12
- ns
- ns
ALE Hold Time
Data Setup Time
tALH
tDS(1)
5
12
- ns
- ns
Data Hold Time
tDH 5
- ns
Write Cycle Time
tWC 25
- ns
WE# High Hold Time
ALE to Data Loading Time
tWH
tADL(2)
10
100
- ns
- ns
Note:
1. The transition of the corresponding control pins must occur only once while WE# is held low.
2. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data
cycle.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. C, Issue Date: 2013/10/03
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet EN27LN1G08.PDF ] |
Número de pieza | Descripción | Fabricantes |
EN27LN1G08 | 3.3V NAND Flash Memory | EON |
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