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CBTL06DP212 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer CBTL06DP212
Beschreibung High-performance DisplayPort Gen2 2 : 1 multiplexer
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 19 Seiten
CBTL06DP212 Datasheet, Funktion
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
Rev. 2 — 3 November 2011
Product data sheet
1. General description
CBTL06DP212 is a high performance multi-channel Generation 2 multiplexer meant for
DisplayPort (DP) v1.2, v1.1a or Embedded DisplayPort applications operating at data rate
of 1.62 Gbit/s, 2.7 Gbit/s or 5.4 Gbit/s. It is designed using NXP proprietary
high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1
multiplexing of four high-speed differential AC-coupled DP channels. Further, it is capable
of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and
Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated
AUX and DDC I/Os, CBTL06DP212 provides an additional level of multiplexing of AUX
and DDC signals delivering true flexibility and choice.
A typical application of CBTL06DP212 is on motherboards where one of two GPU
DisplayPort sources needs to be selected to connect to a DisplayPort sink device or
connector. A controller chip selects which path to use by setting a select signal HIGH or
LOW. Due to the bidirectional nature of the signal paths, CBTL06DP212 can also be used
in the reverse topology, e.g., to connect one display source device to one of two display
sink devices or connectors.
2. Features and benefits
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) signals
4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
main link signals
1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals
1 channel with 2 : 1 multiplexing/switching for HPD signal
High-bandwidth: 5 GHz at 3 dB
Low insertion loss:
0.5 dB at 100 MHz
3 dB at 5 GHz
Low crosstalk: 35 dB at 3 GHz
Low off-state isolation: 30 dB at 3 GHz
Low return loss: 8 dB at 3 GHz
Very low intra-pair skew (5 ps typical)
Very low inter-pair skew (< 80 ps)
Switch/multiplexer position select CMOS input
DDC and AUX ports tolerant to being pulled to +5 V via 2.2 kresistor
Supports HDMI/DVI incorrect dongle connection
Single 3.3 V power supply
Operation current of 2 mA typical






CBTL06DP212 Datasheet, Funktion
NXP Semiconductors
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
Table 3. Pin description …continued
Symbol
Ball Type
DDC_CLK2 H5 differential I/O
DDC_DAT2
J5
differential I/O
AUX+
H2 differential I/O
AUX
H1 differential I/O
HPD_1
J2 single-ended I/O
HPD_2
H3 single-ended I/O
HPDIN
J1 single-ended I/O
VDD
A2, J4 power supply
GND
B3, C8, ground
G2, G8,
H4, H7
Description
Pair of single-ended terminals for DDC clock and data signals,
path 2, left-side.
High-speed differential pair for AUX or single-ended DDC signals,
right-side.
Single ended channel for the HPD signal, path 1, left-side.
Single ended channel for the HPD signal, path 2, left-side.
Single ended channel for the HPD signal, right-side.
3.3 V power supply.
Ground.
8. Functional description
Refer to Figure 1 “Functional diagram”.
The CBTL06DP212 uses a 3.3 V power supply. All main signal paths are implemented
using high-bandwidth pass-gate technology and are bidirectional. No clock or reset signal
is needed for the multiplexer to function.
The switch position for the main channels is selected using the select signal GPU_SEL.
Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the
DDC / AUX channel. The detailed operation is described in Section 8.1.
8.1 Multiplexer/switch select functions
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and
DDC_AUX_SEL as described below.
Table 4. Multiplexer/switch select control for INn and OUTn channels
GPU_SEL
IN1_n
IN2_n
0
active; connected to OUT_n
high-impedance
1 high-impedance
active; connected to OUT_n
Table 5. Multiplexer/switch select control for HPD channel
GPU_SEL
HPD_1
HPD_2
0
active; connected to HPDIN
high-impedance
1 high-impedance
active; connected to HPDIN
CBTL06DP212
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 November 2011
© NXP B.V. 2011. All rights reserved.
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CBTL06DP212 pdf, datenblatt
NXP Semiconductors
CBTL06DP212
High-performance DisplayPort Gen2 2 : 1 multiplexer
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
CBTL06DP212
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 November 2011
© NXP B.V. 2011. All rights reserved.
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