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PCE85176AUG Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCE85176AUG
Beschreibung 4 x 40 LCD segment driver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCE85176AUG Datasheet, Funktion
PCE85176AUG
4 × 40 LCD segment driver for Chip-On-Glass
Rev. 1 — 12 January 2015
Product data sheet
1. General description
The PCE85176AUG is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. The
PCE85176AUG is compatible with most microcontrollers and communicates via the
two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM
with auto-incremented addressing and by display memory switching (static and duplex
drive modes).
For a selection of NXP LCD segment drivers, see Table 31 on page 40.
2. Features and benefits
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 12, or 13
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
Up to 20 7-segment alphanumeric characters
Up to 10 14-segment alphanumeric characters
Any graphics of up to 160 elements
40 4-bit RAM for display data storage
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
From 2.5 V for low-threshold LCDs
Up to 5.5 V for high-threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
No external components required
Compatible with Chip-On-Glass (COG) technology
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.






PCE85176AUG Datasheet, Funktion
NXP Semiconductors
PCE85176AUG
4 × 40 LCD segment driver for Chip-On-Glass
7.1.3 Command: Initialize-RAM
Table 11. Initialize-RAM command bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol
C
1
1
0
0
0
0
0
Table 12. Initialize-RAM command bit description
See Section 7.3.1.
Bit Symbol
Value
Description
7C
0, 1 see Table 6
6 to 0 -
110 0000
initializing the RAM access
7.1.4 Command: bank-select
The bank-select command controls where data is written to RAM and where it is displayed
from.
Table 13. Bank-select command bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol
C
1
1
1
1
0
I
O
Table 14. Bank-select command bit description
See Section 7.3.4.
Bit Symbol
Value
7
6 to 2
1
C
-
I
0O
0, 1
11110
0
1
0
1
Description
Static
1:2 multiplex[1]
see Table 6
fixed value
input bank selection; storage of arriving
display data
RAM row 0
RAM rows 0 and 1
RAM row 2
RAM rows 2 and 3
output bank selection; retrieval of LCD
display data
RAM row 0
RAM rows 0 and 1
RAM row 2
RAM rows 2 and 3
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 48

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PCE85176AUG pdf, datenblatt
NXP Semiconductors
PCE85176AUG
4 × 40 LCD segment driver for Chip-On-Glass
7.3.2 Writing to RAM in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 18 (see Figure 4 as
well).
Table 18. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
012345678
9
:
0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :
1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :
2
a5 a2 -
b5 b2 -
c5 c2 -
d5 :
3 ----------:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 19.
Table 19. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
012345678
9
0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4
1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3
2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2
3 ----------
:
:
:
:
:
In the case described in Table 19 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
In the first write to the RAM, bits a7 to a0 are written.
The data-pointer (see Section 7.3.1 on page 11) has to be set to the address of bit a1
In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
The data-pointer has to be set to the address of bit b1
In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used. But it has to be considered in the module
layout process as well as in the driver software design.
7.3.3 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. In this case, the additional bits will be
discarded.
PCE85176AUG
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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