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PDF CDP68HC68P1 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC68P1 | |
| Descripción | CMOS Serial 8-Bit Input/Output Port | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
CDP68HC68P1
September 2003
FN1858.3
CMOS Serial 8-Bit Input/Output Port
The CDP68HC68P1 is a serially addressed 8-bit
Input/Output port that allows byte or individual bit control. It
consists of three registers, an output buffer and control logic.
Data is shifted in and out of the device via shift register that
utilizes the SPI (Serial Peripheral Interface) bus. The I/O port
data flow is controlled by the Data Direction Register and
data is stored in the Data Register that outputs or senses the
logic levels at the buffered I/O pins. All inputs, including the
serial interface are Schmitt triggered. This device also
features a compare function that compares the data register
and port pin values for 4 programmable conditions and sets
a software accessible flag if the condition is satisfied. The
user also has the option of bit-set or bit-clear when writing to
the data register.
Ordering Information
PART NUMBER
CDP68HC68P1E
CDP68HC68P1M
TEMP.
RANGE (oC) PACKAGE
-55 to 85 16 Ld PDIP
-55 to 85 16 Ld SOIC
PKG.
NO.
E16.3
M16.15
Features
• Fully Static Operation
• Operating Voltage Range 3-6V
• Compatible with Intersil/Motorola SPI Bus
• 2 External Address Pins Tied to VDD or VSS to Allow Up to
4 Devices to Share the Same Chip Enable
• Versatile Bit-Set and Bit-Clear Capability
• Accepts Either SCK Clock Polarity - SCK Voltage Level is
Latched When Chip Enable Goes Active
• All Inputs are Schmitt-Trigger
• 8-Bit I/O Port - Each Bit can be Individually Programmed
as an Input or Output Via an 8-Bit Data Direction Register
• Programmable On Board Comparator
• Simultaneous Transfer of Compare Information to CPU
During Read or Write - Separate Access Not Required
Pinout
CDP68HC68P1
(PDIP, SOIC)
TOP VIEW
ID0 1
ID1 2
MISO 3
MOSI 4
SCK 5
CE 6
DO 7
VSS 8
16 VDD
15 D1
14 D2
13 D3
12 D4
11 D5
10 D6
9 D7
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
Waveforms
MISO
HI Z
CDP68HC68P1
C07 C06
COMPARE FLAG
D7
MOSI
X
CE
SCK
C07 C06
tDVCV
C05
C04
tCVDX
C00
tDVCV
D7
tWL
tEVCV
tWH
tREC
FIGURE 3. PORT-PIN DATA CHANGES
D6
tr, tf
D0
D6 D0
tCVDX
HI Z
X
tCVEX
MOSI
X
C07
C06
C05 C04
C00
X
MISO
CE
SCK
HI Z
tWL
tEVCV
C07 C06
tCVQX
tCVDV
COMPARE FLAG
D7 D6
D0
tEXQZ
HI Z
tWH
tREC
tCVEX
FIGURE 4. READ CYCLE TIMING WAVEFORMS
CE
SCK
(CPOL = 1)
CE
SHIFT INTERNAL
STROBE
SHIFT INTERNAL
STROBE
SCK
(CPOL = 0)
MOSI
OR
MISO
MSB MSB - 1
NOTE: CPOL and CPHA are bits in the CDP68HC05C4B and
CDP68HC05C16B MCU control register and determine inactive
clock polarity and phase. CPHA must always equal 1.
FIGURE 5. DATA TRANSFERS UTILIZING CLOCK INPUT
Introduction
The single port I/O is serially accessed via the synchronous
SPI bus. It features 8 data pins that are programmed as
inputs or outputs. Serial access consists of a two-byte
operation. The first byte shifted in is the control byte that
configures the device. The second byte transferred is the
data byte that is read from or written to the data register or
data direction register. This data byte can also be
programmed to act as a mask to set or clear individual bits.
Functional Description
The single port I/O consists of three byte-wide registers,
(data direction, data and shift) an input/output buffer and
control logic circuitry (See Figure 1). Data is transferred
between the I/O data and data direction registers via the shift
register. Once the I/O port is selected, the first byte shifted in
to the shift register is the control byte that selects the register
(the Data or Data direction register), determines data
transfer direction (read or write) and sets the compare
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CDP68HC68P1.PDF ] | |
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