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CDP1878C Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CDP1878C
Beschreibung CMOS Dual Counter-Timer
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 13 Seiten
CDP1878C Datasheet, Funktion
CDP1878C
March 1997
CMOS Dual Counter-Timer
Features
• Compatible with General Purpose and CDP1800
Series Microprocessor Systems
• Two 16-Bit Down Counters and Two 8-Bit Control
Registers
• 5 Modes Including a Versatile Variable-Duty Cycle
Mode
• Programmable Gate-Level Select
• Two-Complemented Output Pins for Each Counter-
Timer
• Software-Controlled Interrupt Output
• Addressable in Memory Space or CDP1800-Series I/O
Space
Ordering Information
PART
NUMBER
CDP1878CE
CDP1878CD
TEMP. RANGE PACKAGE
-40oC to +85oC PDIP
-40oC to +85oC SBDIP
PKG. NO.
E28.6
N28.6
Description
The CDP1878C is a dual counter-timer consisting of two 16-
bit programmable down counters that are independently
controlled by separate control registers. The value in the reg-
isters determine the mode of operation and control func-
tions. Counters and registers are directly addressable in
memory space by any general industry type microproces-
sors, in addition to input/output mapping with the CDP1800
series microprocessors.
Each counter-timer can be configured in five modes with the
additional flexibility of gate-level control. The control regis-
ters in addition to mode formatting, allow software start and
stop, interrupt enable, and an optional read control that
allows a stable readout from the counters. Each counter-
timer has software control of a common interrupt output with
an interrupt status register indicating which counter-timer
has timed out.
In addition to the interrupt output, true and complemented
outputs are provided for each counter-timer for control of
peripheral devices.
This type is supplied in 28-lead dual-in-line ceramic pack-
ages (D suffix), and 28-lead dual-in-line plastic packages (E
suffix).
Pinout
CDP1878C
(DIP)
TOP VIEW
INT 1
TAO 2
TAO 3
TAG 4
TACL 5
RD 6
IO/MEM 7
TPB/WR 8
TPA 9
CS 10
A0 11
A1 12
A2 13
VSS 14
28 VDD
27 DB7
26 DB6
25 DB5
24 DB4
23 DB3
22 DB2
21 DB1
20 DB0
19 TBO
18 TBO
17 TBG
16 TBCL
15 RESET
TABLE 1. MODE DESCRIPTION
MODE
FUNCTION
APPLICATION
1 Timeout
Outputs change when clock Event counter
decrements counter to “0”
2 Timeout
Strobe
One clockwide output pulse
when clock decrements
counter to “0”
Trigger pulse
3 Gate-Con-
trolled One
Shot
Outputs change when clock
decrements counter to “0”.
Retriggerable
Time-delay
generation
4 Rate Generator Repetitive clockwide output Time-base
pulse
generator
5 Variable-Duty Repetitive output with
Cycle
programmed duty cycle
Motor control
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-91
File Number 1341.2






CDP1878C Datasheet, Funktion
CDP1878C
Bit 3 - Gate Level Select - All modes require an enabling sig-
nal on the gate to allow counter operation. This enabling sig-
nal is either a level or a pulse (edge). Positive gate level or
edge enabling is selected by writing a “1” into this bit and
negative (low) enabling is selected when bit 3 is “0”.
Bit 4 - Interrupt Enable - Setting this bit to “1” enables the
INT output, and setting it to “0” disables it. When reset, the
INT output is at a high level. If the interrupt enable bit in the
control register is enabled and the counter decrements to
zero, the INT output will go low and will not return high until
the counter-timer is reset or the selected control register is
written to. Example: If timer B times out, control register B
must be accessed to reset the INT output high. If the inter-
rupt enable bit is set to “0”, the counter’s timeout will have no
effect on the lNT output.
In mode 5, the variable-duty cycle mode, the lNT pin will
become active low when the MSB in the counter has decre-
mented to zero.
Bit 5 - Start/Stop Control - This bit controls the clock input to
the counter and must be set to “1” to enable it. Writing a “0”
into this location will halt operation of the counter. Operation
will not resume until the bit is set to “1”.
Bit 6 - Holding Register Control - Since the counter may be
decrementing during a read cycle, writing a “1” into this loca-
tion will hold a stable value in the hold register for subse-
quent read operations. Rewriting a “1” into bit 6 will cause an
update in the holding register on the next trailing clock edge.
If this location contains a “0”, the holding register will be
updated continuously by the value in the counter.
Bit 7 - Jam Enable - When this bit is set to “1 “during a write
to the control register, the 16-bit value in the jam register will
be available to the counter; TAO and TBO are reset low and
TAO and TBO are set high. On the trailing edge of the first
input clock signal with the gate valid this value will be latched
in the counter, the counter outputs TAO and TBO will be set
high and the TAO and TBO will be reset low. Setting bit 7 to
“0” will leave the counter value unaffected. This location
should be set to “0” any time a write to the control register
must be performed without changing the present counter
value. If the value in the jam register has not been changed,
writing a “1” into bit 7 of the control register with zeros in bits
0,1, and 2 (mode select) will reload the counter with the old
value and leave the mode unchanged. If the value in the jam
register is changed, then the next write to the control register
(with bit 7 a “1”) must include a valid mode select (i.e., at
least 1 of the bits 0,1, or 2 must be a ”1”).
In mode 3, the hardware start is enabled by writing a “0” into
bit 7. If a “1” is written to bit 7, the timeout will start immedi-
ately and mode 3 will resemble mode 1.
Mode Descriptions
1
MODE
Timeout
CONTROL REGISTER
GATE CONTROL
XXXXX001
BUS 7
BUS 0
Selectable High or Low
Level Enables Operation
Mode 1
After the count is loaded into the jam register and the control
register is written to with the jam-enable bit high on the trail-
ing edge of the first clock after the gate is valid, TXO goes
high and TXO goes low. The input clock decrements the
counter as long as the gate remains valid. When it reaches
zero TXO goes low and TXO goes high, and if enabled, the
interrupt output is set low. Writing to the counter while it is
decrementing has no effect on the counter value unless the
control register is subsequently written to with the jam-
enable bit high. After timeout the counter remains at FFFF
unless reloaded.
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
5432110
5432110
STALL COUNTER
FFFF
GATE
TXO
INT LOAD COUNT = 5
FIGURE 1. TIMEOUT (MODE 1) TIMING WAVEFORMS
4-96

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CDP1878C pdf, datenblatt
CDP1878C
Dynamic Electrical Specifications at TA = -40 to +85oC, VDD = 5V ± 5%, Input tR, tF = 10ns, CL = 50pF and 1 TTL Load
PARAMETER
SYMBOL
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
UNITS
READ CYCLE TIMES (See Figure 14)
Data Access from Address tDA -
Read Pulse Width
tRD 400
Data Access from Read
tDR -
Address Hold after Read
tRH 0
Output Hold after Read
tDH 50
Chip Select Setup to TPA
tCS 50
NOTES:
1. Time required be a limit device to allow for the indicated function.
2. Typical values are for TA = 25oC and nominal VDD.
350
-
250
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
TPA
ADDRESS/CHIP SELECT
READ
DATA TO CPU
tCS tRH
tRD
tDR
tDA
tDH
FIGURE 14. READ CYCLE TIMING WAVEFORMS
4-102

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