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CDP1855C Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CDP1855C
Beschreibung 8-Bit Programmable Multiply/Divide Unit
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 15 Seiten
CDP1855C Datasheet, Funktion
March 1997
CDP1855,
CDP1855C
8-Bit Programmable
Multiply/Divide Unit
Features
• Cascadable Up to 4 Units for 32-Bit by 32-Bit Multiply
÷or 64 32-Bit Divide
÷• 8-Bit by 8-Bit Multiply or 16 8-Bit Divide in 5.6µs at
5V or 2.8µs at 10V
• Direct Interface to CDP1800-Series Microprocessors
• Easy Interface to Other 8-Bit Microprocessors
• Significantly Increases Throughput of Microprocessor
Used for Arithmetic Calculations
Ordering Information
PACKAGE TEMP. RANGE
5V
PDIP
-40oC to +85oC CDP1855CE
PKG.
10V NO.
CDP1855E E28.6
Burn-In
SBDIP
CDP1855CEX - E28.6
-40oC to +85oC CDP1855CD CDP1855D D28.6
Burn-In
CDP1855CDX - D28.6
Description
The CDP1855 and CDP1855C are CMOS 8-bit multi-
ply/divide units which can be used to greatly increase the
capabilities of 8-bit microprocessors. They perform multiply
and divide operations on unsigned, binary operators. In
general, microprocessors do not contain multiply or divide
instructions and even efficiently coded multiply or divide
subroutines require considerable memory and execution
time. These multiply/divide units directly interface to the
CDP1800-series microprocessors via the N-lines and can
easily be configured to fit in either the memory or I/O space
of other 8-bit microprocessors.
The multiple/divide unit is based on a method of multiplying
by add and shift right operations and dividing by subtract and
shift left operations. The device is structured to permit cas-
cading identical units to handle operands up to 32 bits.
The CDP1855 and CDP1855C are functionally identical.
They differ in that the CDP1855 has a recommended
operating voltage range of 4V to 10.5V, and the CDP1855C,
a recommended operating voltage range of 4V to 6.5V.
The CDP1855 and CDP1855C types are supplied in a 28
lead hermetic dual-in-line ceramic package (D suffix) and in
a 28 lead dual-in-line plastic package (E suffix). The
CDP1855C is also available in chip form (H suffix).
Pinout
28 LEAD DIP
TOP VIEW
Circuit Configuration
+V
CE 1
CLEAR 2
CTL 3
C.O./O.F. 4
YL 5
ZL 6
SHIFT 7
CLK 8
STB 9
RD/WE 10
RA2 11
RA1 12
RA0 13
VSS 14
28 VDD
27 CN0
26 CN1
25 CI
24 YR
23 ZR
22 BUS 7
21 BUS 6
20 BUS 5
19 BUS 4
18 BUS 3
17 BUS 2
16 BUS 1
15 BUS 0
CLEAR
XTAL
N0
N1
N2
TPB
MRD
CDP1802
EF
BUS
CLEAR
CLK
CE
RA0
C1
RA1
CN0
RA2
CN1
STB
RD/WE
CDP1855
YL
ZR
CTL
C0
YR
ZL
BUS
FIGURE 1. MDU ADDRESSED AS I/O DEVICE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-47
File Number 1053.2






CDP1855C Datasheet, Funktion
CDP1855, CDP1855C
RD/WE - Read/Write Enable (Input):
This signal defines whether the selected register is to be
read from or written to. In 1800 systems use MRD if MDU's
are addressed as I/O devices, MWR is used if MDU's are
addressed as memory devices.
RA2, RA1, RA0 - Register Address (Input):
These input signals define which register is to be read from
or written to. It can be seen in the “CONTROL TRUTH
TABLE” that RA2 can be used as a chip enable. It is identical
to the CE pin, except only CE controls the three-state
C.O./O.F. on the most significant MDU. In 1800 systems use
N lines if MDU's are used as I/O devices, use address lines
or function of address lines if MDU's are used as memory
devices.
Bus 0 - Bus 7 - Bus Lines:
Three-state bi-directional bus for direct interface with
CDP1800 series and other 8-bit microprocessors.
ZR - Z-Right:
See Pin 6.
YR - Y-Right:
See Pin 5.
Cl- Carry In (Input):
This is an input for the carry from the next less significant
MDU. On the least significant MDU it must be high (VDD) on
all others it must be connected to the CO pin of the next less
significant MDU.
CN1, CN0 - Chip Number (Input):
These two input pins are wired high or low to indicate the
MDU position in the cascaded chain. Both are high for the
most significant MDU regardless of how many CDP1855
MDU's are used. Then CN1 = high and CN0 = low for the
next MDU and so forth.
VSS - Ground:
Power supply line.
VDD - V+:
Power supply line.
CONTROL TRUTH TABLE
INPUTS (NOTE 1)
RA2
RA1
RA0
RD/WE
STB
CE
(N2)
(N1)
(N0)
(MRD)
(TPB)
RESPONSE
0 X X X X X No Action (Bus Floats)
X 0 X X X X No Action (Bus Floats)
1 1 0 0 1 X X to Bus
1 1 0 1 1 X Z to Bus
1 1 1 0 1 X Y to Bus
Increment Sequence
Counter When STB
and RD = 1
1 1 1 1 1 X Status to Bus
1 1 0 0 0 1 Load X from Bus
1
1
0
1
0
1 Load Z from Bus
Increment Sequence
Counter
1 1 1 0 0 1 Load Y from Bus
1 1 1 1 0 1 Load Control Register
1 1 X X 0 0 No Action (Bus Floats)
NOTE:
1. ( ) = 1800 System Signals. 1 = High Level, 0 = Low Level, X = High or Low Level.
4-52

6 Page









CDP1855C pdf, datenblatt
CDP1855, CDP1855C
Dynamic Electrical Specifications At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, VIH = 0.7VDD, VIL = 0.3VDD,
CL = 100pF (See Figure 7)
LIMITS
CDP1855
CDP1855C
(NOTE 1)
PARAMETER
VDD
(V)
(NOTE 2)
MIN TYP MAX
(NOTE 2)
MIN
TYP
MAX
UNITS
OPERATION TIMING
Maximum Clock Frequency
(Note 3)
5 3.2
10 6.4
4
8
- 3.2
--
4
-
- MHz
- MHz
Maximum Shift Frequency
(1 Device) (Note 4)
5 1.6
10 3.2
2
4
- 1.6
--
2
-
- MHz
- MHz
Minimum Clock Width
tCLK0
tCLK1
5
10
-
-
100 150
50 75
-
-
100 150 ns
- - ns
Minimum Clock Period
tCLK
5
10
-
-
250 312
125 156
-
-
250 312 ns
- - ns
Clock to Shift Propagation
Delay
tCSH
5
10
-
-
200 300
100 150
-
-
200 300 ns
- - ns
Minimum C.I. to Shift Setup
tSU
5
10
-
-
50 67 -
25 33 -
50 67 ns
- - ns
C.O. from Shift Propagation
Delay
tPLH
tPHL
5
10
-
-
450 600
225 300
-
-
450 600 ns
- - ns
Minimum C.I. from Shift Hold
tH
5
10
-
-
50 75 -
25 40 -
50 75 ns
- - ns
Minimum Register Input
Setup
tSU 5
10
-
-
-20 10
-10 10
-
-
-20 10 ns
- - ns
Register after Shift Delay
tPLH
tPHL
5
10
-
-
400 600
200 300
-
-
400 600 ns
- - ns
Minimum Register after Shift
Hold
tH
5
10
-
-
50 100 -
25 50 -
50 100 ns
- - ns
C.O. from C.I. Propagation
Delay
tPLH
tPHL
5
10
-
-
100 150
50 75
-
-
100 150 ns
- - ns
Register from C.I.
Propagation Delay
tPLH
tPHL
5
10
-
-
80 120 -
40 60 -
80 120 ns
- - ns
NOTES:
1. Maximum limits of minimum characteristics are the values above which all devices function.
2. Typical values are for TA = 25oC and nominal voltages.
3. Clock frequency and pulse width are given for systems using the internal clock option of the CDP1855. Clock frequency equals shift
frequency for systems not using the internal clock option.
4. Shift period for cascading of devices is increased by an amount equal to the C.I. to C.O. Propagation Delay for each device added.
4-58

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