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PDF CDP1805AC Data sheet ( Hoja de datos )
| Número de pieza | CDP1805AC | |
| Descripción | CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer | |
| Fabricantes | Intersil Corporation | |
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TM
March 1997
CDP1805AC,
CDP1806AC
CMOS 8-Bit Microprocessor with On-Chip RAM†
and Counter/Timer
Features
• Instruction Time of 3.2µs, -40oC to +85oC
• 123 Instructions - Upwards Software Compatible With
CDP1802
• BCD Arithmetic Instructions
• Low-Power IDLE Mode
• Pin Compatible With CDP1802 Except for Terminal 16
• 64K-Byte Memory Address Capability
• 64 Bytes of On-Chip RAM†
• 16 x 16 Matrix of On-Board Registers
• On-Chip Crystal or RC Controlled Oscillator
• 8-Bit Counter/Timer
n
Description
The CDP1805AC and CDP1806AC are functional and per-
formance enhancements of the CDP1802 CMOS 8-bit regis-
ter-oriented microprocessor series and are designed for use
in general-purpose applications.
The CDP1805AC hardware enhancements include a 64-
byte RAM and an 8-bit presettable down counter. The
Counter/Timer which generates an internal interrupt request,
can be programmed for use in timebase, event-counting,
and pulse-duration measurement applications. The
Counter/Timer underflow output can also be directed to the
Q output terminal. The CDP1806AC hardware enhance-
ments are identical to the CDP1805AC, except the
CDP1806AC contains no on-chip RAM.
The CDP1805AC and CDP1806AC software enhancements
include 32 more instructions than the CDP1802. The 32 new
software instructions add subroutine call and return capabil-
ity, enhanced data transfer manipulation, Counter/Timer con-
trol, improved interrupt handling, single-instruction loop
counting, and BCD arithmetic.
Upwards software and hardware compatibility is maintained
when substituting a CDP1805AC or CDP1806AC for other
CDP1800-series microprocessors. Pinout is identical except
for the replacement of VCC with ME on the CDP1805AC and
the replacement of VCC with VDD on the CDP1806AC.
Ordering Information
CDP1805AC
CDP1805ACE
-
CDP1805ACQ
CDP1805ACD
CDP1805ACDX
CDP1806AC
CDP1806ACE
CDP1806ACEX
CDP1806ACQ
CDP1806ACD
-
TEMPERATURE RANGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
PACKAGE
Plastic DIP
Burn-In
PLCC
SBDIP
Burn-In
PKG. NO.
E40.6
N44.65
D40.6
† CDP1805AC Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
File Number 1370.2
1 page  
CDP1805AC, CDP1806AC
Static Electrical Specifications at TA = -40oC to +85oC, VDD ±5%, Except as Noted (Continued)
CDP1805ACD, CDP1805ACE
CDP1806ACD, CDP1806ACE
PARAMETER
VO VIN VDD
(NOTE 3)
(V) (V) (V) MIN
TYP
MAX UNITS
Input Low Voltage (BUS0 - BUS7, ME), VIL
0.5, 4.5
-
5
-
- 1.5 V
Input High Voltage (BUS0 - BUS7, ME), VIH
0.5, 4.5
-
5 3.5
-
-V
Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME)
Positive Trigger Threshold, VP
0.5, 4.5
-
5 2.2 2.9
3.6 V
Negative Trigger Threshold, VN
0.5, 4.5
-
5 0.9 1.9
2.8 V
Hysteresis, VH
0.5, 4.5
-
5 0.3 0.9
1.6 V
Input Leakage Current, IIN
- 0, 5 5 - ±0.1 ±5 µA
Three-State Output Leakage Current, IOUT
0, 5 0, 5
5
-
±0.2 ±5 µA
Input Capacitance, CIN
--- -
5 7.5 pF
Output Capacitance, COUT
- - - - 10 15 pF
Total Power Dissipation (Note 4)
Run
- -5 -
35 50 mW
Idle “00” at M (0000)
- -5 -
12 18 mW
Minimum Data Retention Voltage, VDR
Data Retention Current, IDR
NOTES:
3. Typical values are for TA = +25oC and nominal VDD.
4. External clock: f = 5MHz, t R, t F = 10ns; CL = 50pF.
VDD = VDR
VDD = 2.4
- 2 2.4 V
- 25 100 µA
Dynamic Electrical Specifications at TA = -40o to +85oC; C L = 50pF; Input tR, tF = 10ns; Input Pulse Levels = 0.1V to
VDD -0.1V; VDD = 5V, ±5%.
CDP1805AC CDP1806AC
PARAMETER
(NOTE 5)
TYP
MAX
UNITS
Propagation Delay Times
Clock to TPA, TPB, tPLH, tPHL
Clock-to-Memory High-Address Byte, tPLH, tPHL
Clock-to-Memory Low-Address Byte, tPLH, tPHL
Clock to MRD, tPLH, tPHL
Clock to MWR, tPLH, tPHL (See Note 5)
Clock to (CPU DATA to BUS), tPLH, tPHL
Clock to State Code, tPLH, tPHL
Clock to Q, tPLH, tPHL
Clock to N, tPLH, tPHL
Clock to Internal RAM Data to BUS, tPLH, tPHL
150 275
325 550
275 450
200 325
150 275
375 625
225 400
250 425
250 425
420 650
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5 Page 
CDP1805AC, CDP1806AC
The X designator selects one of the 16 registers R(X) to
“point” to the memory for an operand (or data) in certain ALU
or I/O operations.
The N designator can perform the following five functions
depending on the type of instruction fetched:
1. Designate one of the 16 registers in R to be acted upon
during register operations.
2. Indicate to the I/O devices a command code or device-
selection code for peripherals.
3. Indicate the specific operation to be executed during the
ALU instructions, types of tests to be performed during
the Branch instructions, or the specific operation required
in a class of miscellaneous instructions.
4. Indicate the value to be loaded into P to designate a new
register to be used as the program counter R(P).
5. Indicate the value to be loaded into X to designate a new
register to be used as data pointer R(X).
The registers in R can be assigned by a programmer in three
different ways as program counters, as data pointers, or as
scratchpad locations (data registers) to hold two bytes of
data.
Program Counters
Any register can be the main program counter; the address
of the selected register is held in the P designator. Other reg-
isters in R can be used as subroutine program counters. By
a single instruction the contents of the P register can be
changed to effect a “call” to subroutine. When interrupts are
being serviced, register R(1) is used as the program counter
for the user's interrupt servicing routine. After reset, and dur-
ing a DMA operation, R(0) is used as the program counter.
At all other times the register designated as program counter
is at the discretion of the user.
Data Pointers
The registers in R may be used as data pointers to indicate a
location in memory. The register designated by X (i.e., R(X))
points to memory for the following instructions (see Table 1):
1. ALU operations.
2. Output instructions.
3. Input instructions.
4. Register to memory transfer.
5. Memory to register transfer.
6. Interrupt and subroutine handling.
The register designated by N (i.e., R(N)) points to memory
for the “load D from memory” instructions ON and 4N and
the “Store D” instruction 5N. The register designated by P
(i.e., the program counter) is used as the data pointer for
ALU instructions F8-FD, FF, 7C, 7D, 7F, and the RLDl
instruction 68CN. During these instruction executions, the
operation is referred to as “data immediate”.
Another important use of R as a data pointer supports the
built-in Direct-Memory-Access (DMA) function. When a
DMA-ln or DMA-Out request is received, one machine cycle
is “stolen”. This operation occurs at the end of the execute
machine cycle in the current instruction. Register R(0) is
always used as the data pointer during the DMA operation.
The data is read from (DMA-Out) or written into (DMA-ln) the
memory location pointed to by the R(0) register. At the end
of the transfer, R(0) is incremented by one so that the pro-
cessor is ready to act upon the next DMA byte transfer
request. This feature in the CDP1805AC and CDP1806AC
architecture saves a substantial amount of logic when fast
exchanges of blocks of data are required, such as with mag-
netic discs or during CRT-display-refresh cycles.
Data Registers
When registers in R are used to store bytes of data, instruc-
tions are provided which allow D to receive from or write into
either the higher-order- or lower-order-byte portions of the
register designated by N. By this mechanism (together with
loading by data immediate) program pointer and data pointer
designations are initialized. Also, this technique allows
scratchpad registers in R to be used to hold general data. By
employing increment or decrement instructions, such regis-
ters may be used as loop counters. The new RLDl, RLXA,
RSXD, and RNX instructions also allow loading, storing, and
exchanging the full 16-Bit contents of the R registers without
affecting the D register. The new DBNZ instruction allows
decrementing and branching-on-not-zero of any 16-Bit R
register also without affecting the D register.
The Q Flip-Flop
An internal flip-flop, Q, can be set or reset by instruction and
can be sensed by conditional branch instructions. It can also
be driven by the underflow output of the counter/timer The
output of Q is also available as a microprocessor output.
REGISTER SUMMARY
D
DF
B
R
P
X
N
I
T
Q
CNTR
CH
MIE
ClE
XlE
ClL
8 Bits Data Register (Accumulator)
1-Bit Data Flag (ALU Carry)
8 Bits Auxiliary Holding Register
16 Bits 1 of 16 Scratch and Registers
4 Bits Designates which Register is Program
Counter
4 Bits Designates which Register is Data Pointer
4 Bits Holds Low-Order Instr. Digit
4 Bits Holds High-Order Instr. Digit
8 Bits Holds old X, P after Interrupt (X is high nibble)
1-Bit Output Flip-Flop
8-Bits Counter/Timer
8 Bits Holds Counter Jam Value
1-Bit Master Interrupt Enable
1-Bit Counter Interrupt Enable
1-Bit External Interrupt Enable
1-Bit Counter Interrupt Latch
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CDP1805AC.PDF ] | |
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