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ADSP-BF512 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-BF512
Beschreibung Blackfin Embedded Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-BF512 Datasheet, Funktion
Blackfin
Embedded Processor
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
FEATURES
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages. See Operating Conditions
on Page 22
Qualified for Automotive Applications. See Automotive
Products on Page 67
168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad)
MEMORY
116K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Optional 16M bit SPI flash with boot option
Flexible booting options from internal SPI flash, OTP
memory, external SPI/parallel memories, or from SPI/UART
host devices
Code security with Lockbox secure technology
One-time-programmable (OTP) memory
Memory management unit providing memory protection
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588
support (ADSP-BF518/ADSP-BF518F16 only)
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 56 interrupt inputs
2 serial peripheral interfaces (SPI)
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
3-phase 16-bit center-based PWM unit
32-bit general-purpose counter
Real-time clock (RTC) and watchdog timer
32-bit core timer
40 general-purpose I/Os (GPIOs)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
RTC
OTP
WATCHDOG TIMER
PERIPHERAL
ACCESS BUS
JTAG TEST AND EMULATION
B
INTERRUPT
CONTROLLER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
DMA
CONTROLLER
16 DMA CORE BUS
EXTERNAL ACCESS BUS
DMA
EXTERNAL
BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT
ROM
COUNTER
3-PHASE PWM
TIMER7–0
TWI
SPORT1-0
RSI (SDIO)
PPI
UART1–0
EMAC
SPI1
SPI0
16M bit SPI Flash
(See Table 1)
Figure 1. Functional Block Diagram
PORTS
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. D
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Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADSP-BF512 Datasheet, Funktion
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
The processors internally connect to the flash memory die with
the SPI0SCK, SPI0SEL4 or PH8, SPI0MOSI, and SPI0MISO sig-
nals similar to an external SPI flash (for signal descriptions, see
Table 2). To further provide a secure processing environment,
these internally connected signals are not exposed outside of the
package. For this reason, programming the ADSP-BF51xF flash
memory is performed by running code on the processor and
cannot be programmed from external signals. Data transfers
between the SPI flash and the processor cannot be probed exter-
nally. The flash memory has the following additional features.
• Serial Interface Architecture—SPI compatible with Mode 0
and Mode 3
• Flexible Erase Capability—Uniform 4K Byte sectors and
uniform 64K Byte overlay blocks
• Fast Erase and Byte-Program—Chip-erase time = 11.2 s
(typical), Sector-/Block-Erase Time = 70/350 ms (typical)
Byte-Program Time = 15 μS (typical)
• Software Write Protection—Write protection through
block-protection bits in status register
Combinational Logic
Truth Table
SEL4 or PH8 MISO_EXT, SPICLK_EXT, MOSI_EXT
0 Three-state
1 As programmed
ADSP-BF51xF
Package
Signals between the processor and the flash
operate at the VDDFLASH voltage level.
SPI Flash Die
SO
SCK
SI
CE
VDD
GND
RST
VDDFLASH
GND
RESET
ADSP-BF51x Die
SPI0
MISO
SPICLK
MOSI
SEL4
SPISS
SEL4
PH8
Combinational Logic
MISO_INT
SPICLK_INT
MOSI_INT
SEL4
SPISS
MISO_EXT
SPICLK_EXT
MOSI_EXT
RESET
M
U
X
L
O
G
I
C
SPI0 signals external
to the processor
operate at the
VDDEXT voltage
level.
PG13-SPI0MISO
PG12-SPI0SCK
PG14-SPI0MOSI
PG11-SPI0SS
Figure 4. Flash Memory Block Diagram
Rev. D | Page 6 of 68 | April 2014

6 Page









ADSP-BF512 pdf, datenblatt
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
Parallel Peripheral Interface (PPI)
The ADSP-BF51x processors provide a parallel peripheral inter-
face (PPI) that can connect directly to parallel analog-to-digital
and digital-to-analog converters, ITU-R-601/656 video encod-
ers and decoders, and other general-purpose peripherals. The
PPI consists of a dedicated input clock signal, up to three frame
synchronization signals, and up to 16 data signals.
In ITU-R-656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information
is supported.
Three distinct ITU-R-656 modes are supported:
• Active video only mode—The PPI does not read in any
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI.
• Vertical blanking only mode—The PPI only transfers verti-
cal blanking interval (VBI) data, as well as horizontal
blanking information and control byte sequences on
VBI lines.
• Entire field mode—The entire incoming bitstream is read
in through the PPI. This includes active video, control pre-
amble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R-656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
These modes support ADC/DAC connections, as well as video
communication with hardware signalling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
Code Security with Lockbox Secure Technology
A security system consisting of a blend of hardware and soft-
ware provides customers with a flexible and rich set of code
security features with Lockbox® secure technology. Key features
include:
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets.
DYNAMIC POWER MANAGEMENT
The ADSP-BF51x processors provide four operating modes,
each with a different performance/power profile. In addition,
dynamic power management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. When configured for a 0 V core
supply voltage, the processor enters the hibernate state. Control
of clocking to each of the processor peripherals also reduces
power consumption. See Table 3 for a summary of the power
settings for each mode.
Table 3. Power Settings
Mode/State PLL
Core
PLL Clock
Bypassed (CCLK)
System
Clock Core
(SCLK) Power
Full On
Enabled No
Enabled Enabled On
Active
Enabled/ Yes
Disabled
Enabled Enabled On
Sleep
Enabled —
Disabled Enabled On
Deep Sleep Disabled —
Disabled Disabled On
Hibernate Disabled —
Disabled Disabled Off
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
Rev. D | Page 12 of 68 | April 2014

12 Page





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