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PDF ADSP-BF707 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-BF707 | |
| Descripción | Blackfin+ Core Embedded Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
FEATURES
Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),
RoHS compliant
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION
PERIPHERALS FEATURES
See Figure 1, Processor Block Diagram and Table 1, Processor
Comparison
MEMORY
136 kB L1 SRAM with multi-parity-bit protection
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz)
Security and one-time-programmable memory
Crypto hardware accelerators
Fast secure boot for IP protection
memDMA encryption/decryption for fast run-time security
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
SYSTEM CONTROL BLOCKS
EVENT
CONTROL
WATCHDOG
PERIPHERALS
1× TWI
8× TIMER
1× COUNTER
B
136K BYTE PARITY BIT PROTECTED
L1 SRAM INSTRUCTION/DATA
L2 MEMORY
512K BYTE
ROM
UP TO
1M BYTE SRAM
ECC-PROTECTED
(& DMA MEMORY
PROTECTION)
EXTERNAL
BUS
INTERFACES
MEMORY
PROTECTION
DYNAMIC MEMORY
CONTROLLER
SYSTEM FABRIC
OTP
MEMORY
HARDWARE
FUNCTIONS
ANALOG
SUB
SYSTEM
SYSTEM PROTECTION
CRYPTO ENGINE (SECURITY)
HADC
2× CAN
2× UART
SPI HOST PORT
2x QUAD SPI
1x DUAL SPI
GPIO
2× SPORT
1× MSI
(SD/SDIO)
1× PPI
STATIC MEMORY
CONTROLLER
3× MDMA
STREAMS
2× CRC
1× RTC
LPDDR
DDR2
16
1× USB 2.0 HS OTG
Figure 1. Processor Block Diagram
Blackfin+ is a trademark of Analog Devices, Inc.; Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADSP-BF700/701/702/703/704/705/706/707
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with dynamic branch prediction),
and subroutine calls. Hardware supports zero-overhead loop-
ing. The architecture is fully interlocked, meaning that the
programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The Blackfin processor supports a modified Harvard architec-
ture in combination with a hierarchical memory structure. Level
1 (L1) memories are those that typically operate at the full pro-
cessor speed with little or no latency. At the L1 level, the
instruction memory holds instructions only. The data memory
holds data, and a dedicated scratchpad data memory stores
stack and local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
INSTRUCTION SET DESCRIPTION
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. The Blackfin proces-
sor supports a limited multi-issue capability, where a 32-bit
instruction can be issued in parallel with two 16-bit instruc-
tions, allowing the programmer to use many of the core
resources in a single instruction cycle.
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• Control of all asynchronous and synchronous events to the
processor is handled by two subsystems: the core event
controller (CEC) and the system event controller (SEC).
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
PROCESSOR INFRASTRUCTURE
The following sections provide information on the primary
infrastructure components of the ADSP-BF70x processor.
DMA Controllers
The processor uses direct memory access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processor can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of proces-
sor activity.
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each memory-to-
memory DMA stream uses two channels, where one channel is
the source channel, and the second is the destination channel.
All DMAs can transport data to and from all on-chip and off-
chip memories. Programs can use two types of DMA transfers,
descriptor-based or register-based. Register-based DMA allows
the processor to directly program DMA control registers to ini-
tiate a DMA transfer. On completion, the control registers may
be automatically updated with their original setup values for
continuous transfer. Descriptor-based DMA transfers require a
set of parameters stored within memory to initiate a DMA
sequence. Descriptor-based DMA transfers allow multiple
DMA sequences to be chained together and a DMA channel can
be programmed to automatically set up and start another DMA
transfer after the current sequence completes.
The DMA controller supports the following DMA operations.
• A single linear buffer that stops on completion.
• A linear buffer with negative, positive, or zero stride length.
• A circular, auto-refreshing buffer that interrupts when each
buffer becomes full.
Rev. A | Page 5 of 116 | September 2015
5 Page 
ADSP-BF700/701/702/703/704/705/706/707
Serial Peripheral Interface (SPI) Ports
The processors have three industry-standard SPI-compatible
ports that allow it to communicate with multiple SPI-compati-
ble devices.
The baseline SPI peripheral is a synchronous, four-wire inter-
face consisting of two data pins, one device select pin, and a
gated clock pin. The two data pins allow full-duplex operation
to other SPI-compatible devices. An additional two (optional)
data pins are provided to support quad SPI operation. Enhanced
modes of operation such as flow control, fast mode, and dual
I/O mode (DIOM) are also supported. In addition, a direct
memory access (DMA) mode allows for transferring several
words with minimal CPU interaction.
With a range of configurable options, the SPI ports provide a
glueless hardware interface with other SPI-compatible devices
in master mode, slave mode, and multimaster environments.
The SPI peripheral includes programmable baud rates, clock
phase, and clock polarity. The peripheral can operate in a multi-
master environment by interfacing with several other devices,
acting as either a master device or a slave device. In a multimas-
ter environment, the SPI peripheral uses open-drain outputs to
avoid data bus contention. The flow control features enable slow
slave devices to interface with fast master devices by providing
an SPI Ready pin which flexibly controls the transfers.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has integrated DMA channels for both
transmit and receive data streams.
SPI Host Port (SPIHP)
The processor includes one SPI host port which may be used in
conjunction with any available SPI port to enhance its SPI slave
mode capabilities. The SPIHP allows a SPI host device access to
memory-mapped resources of the processor through a SPI
SRAM/FLASH style protocol. The following features are
included:
• Direct read/write of memory and memory-mapped
registers
• Support for pre-fetch for faster reads
• Support for SPI controllers that implement hardware-
based SPI memory protocol
• Error capture and reporting for protocol errors, bus errors,
and over/underflow
UART Ports
The processor provides two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
and none, even, or odd parity. Optionally, an additional address
bit can be transferred to interrupt only addressed nodes in
multi-drop bus (MDB) systems. A frame is terminated by a con-
figurable number of stop bits.
The UART ports support automatic hardware flow control
through the clear to send (CTS) input and request to send (RTS)
output with programmable assertion FIFO levels.
To help support the local interconnect network (LIN) protocols,
a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable inter-frame space.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
2-Wire Controller Interface (TWI)
The processor includes a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI module is compatible with the
widely used I2C bus standard. The TWI module offers the
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitra-
tion. The TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compati-
ble with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
Mobile Storage Interface (MSI)
The mobile storage interface (MSI) controller acts as the host
interface for multimedia cards (MMC), secure digital memory
cards (SD), and secure digital input/output cards (SDIO). The
following list describes the main features of the MSI controller:
• Support for a single MMC, SD memory, and SDIO card
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit, and 8-bit MMC modes
• Support for eMMC 4.5 embedded NAND flash devices
• Support for power management and clock control
• An eleven-signal external interface with clock, command,
optional interrupt, and up to eight data lines
• Card interface clock generation from SCLK0 or SCLK1
• SDIO interrupt and read wait features
Controller Area Network (CAN)
A CAN controller implements the CAN 2.0B (active) protocol.
This protocol is an asynchronous communications protocol
used in both industrial and automotive control systems. The
CAN protocol is well suited for control applications due to its
capability to communicate reliably over a network. This is
because the protocol incorporates CRC checking, message error
tracking, and fault node confinement.
Rev. A | Page 11 of 116 | September 2015
11 Page | ||
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| PDF Descargar | [ Datasheet ADSP-BF707.PDF ] | |
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