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ADSP-BF704 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-BF704
Beschreibung Blackfin+ Core Embedded Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-BF704 Datasheet, Funktion
Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
FEATURES
Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),
RoHS compliant
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION
PERIPHERALS FEATURES
See Figure 1, Processor Block Diagram and Table 1, Processor
Comparison
MEMORY
136 kB L1 SRAM with multi-parity-bit protection
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz)
Security and one-time-programmable memory
Crypto hardware accelerators
Fast secure boot for IP protection
memDMA encryption/decryption for fast run-time security
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
SYSTEM CONTROL BLOCKS
EVENT
CONTROL
WATCHDOG
PERIPHERALS
1× TWI
8× TIMER
1× COUNTER
B
136K BYTE PARITY BIT PROTECTED
L1 SRAM INSTRUCTION/DATA
L2 MEMORY
512K BYTE
ROM
UP TO
1M BYTE SRAM
ECC-PROTECTED
(& DMA MEMORY
PROTECTION)
EXTERNAL
BUS
INTERFACES
MEMORY
PROTECTION
DYNAMIC MEMORY
CONTROLLER
SYSTEM FABRIC
OTP
MEMORY
HARDWARE
FUNCTIONS
ANALOG
SUB
SYSTEM
SYSTEM PROTECTION
CRYPTO ENGINE (SECURITY)
HADC
2× CAN
2× UART
SPI HOST PORT
2x QUAD SPI
1x DUAL SPI
GPIO
2× SPORT
1× MSI
(SD/SDIO)
1× PPI
STATIC MEMORY
CONTROLLER
3× MDMA
STREAMS
2× CRC
1× RTC
LPDDR
DDR2
16
1× USB 2.0 HS OTG
Figure 1. Processor Block Diagram
Blackfin+ is a trademark of Analog Devices, Inc.; Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
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ADSP-BF704 Datasheet, Funktion
ADSP-BF700/701/702/703/704/705/706/707
• A similar buffer that interrupts on fractional buffers (for
example, 1/2, 1/4).
• 1D DMA—uses a set of identical ping-pong buffers defined
by a linked ring of two-word descriptor sets, each contain-
ing a link pointer and an address.
• 1D DMA—uses a linked list of 4 word descriptor sets con-
taining a link pointer, an address, a length, and a
configuration.
• 2D DMA—uses an array of one-word descriptor sets, spec-
ifying only the base DMA address.
• 2D DMA—uses a linked list of multi-word descriptor sets,
specifying everything.
Event Handling
The processor provides event handling that supports both nest-
ing and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher-priority event takes precedence over ser-
vicing of a lower-priority event. The processor provides support
for five different types of events:
• Emulation—An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor through the JTAG interface.
• Reset—This event resets the processor.
• Nonmaskable interrupt (NMI)—The NMI event can be
generated either by the software watchdog timer, by the
NMI input signal to the processor, or by software. The
NMI event is frequently used as a power-down indicator to
initiate an orderly shutdown of the system.
• Exceptions—Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts —Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
System Event Controller (SEC)
The SEC manages the enabling, prioritization, and routing of
events from each system interrupt or fault source. Additionally,
it provides notification and identification of the highest priority
active system interrupt request to the core and routes system
fault sources to its integrated fault management unit. The SEC
triggers core general-purpose interrupt IVG11. It is recom-
mended that IVG11 be set to allow self-nesting. The four lower
priority interrupts (IVG15-12) may be used for software
interrupts.
Trigger Routing Unit (TRU)
The TRU provides system-level sequence control without core
intervention. The TRU maps trigger masters (generators of trig-
gers) to trigger slaves (receivers of triggers). Slave endpoints can
be configured to respond to triggers in various ways. Common
applications enabled by the TRU include:
• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes
• Software triggering
• Synchronization of concurrent activities
General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled by
manipulation of the port control, status, and interrupt registers:
• GPIO direction control register—Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers—A write one to modify
mechanism allows any combination of individual GPIO
pins to be modified in a single instruction, without affect-
ing the level of any other GPIO pins.
• GPIO interrupt mask registers—Allow each individual
GPIO pin to function as an interrupt to the processor.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers—Specify whether indi-
vidual pins are level- or edge-sensitive and specify—if
edge-sensitive—whether just the rising edge or both the ris-
ing and falling edges of the signal are significant.
Pin Interrupts
Every port pin on the processor can request interrupts in either
an edge-sensitive or a level-sensitive manner with programma-
ble polarity. Interrupt functionality is decoupled from GPIO
operation. Three system-level interrupt channels (PINT0–3) are
reserved for this purpose. Each of these interrupt channels can
manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed on a pin-by-pin basis. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
Every pin interrupt channel features a special set of 32-bit mem-
ory-mapped registers that enable half-port assignment and
interrupt management. This includes masking, identification,
and clearing of requests. These registers also enable access to the
respective pin states and use of the interrupt latches, regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
Pin Multiplexing
The processor supports a flexible multiplexing scheme that mul-
tiplexes the GPIO pins with various peripherals. A maximum of
4 peripherals plus GPIO functionality is shared by each GPIO
pin. All GPIO pins have a bypass path feature—that is, when the
Rev. A | Page 6 of 116 | September 2015

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ADSP-BF704 pdf, datenblatt
ADSP-BF700/701/702/703/704/705/706/707
The CAN controller offers the following features:
• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-
rable for receive or transmit)
• Dedicated acceptance masks for each mailbox
• Additional data filtering on first two bytes
• Support for both the standard (11-bit) and extended
(29-bit) identifier (ID) message formats
• Support for remote frames
• Active or passive network support
• CAN wake-up from hibernation mode (lowest static power
consumption mode)
• Interrupts, including: TX complete, RX complete, error
and global
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from a system clock through a pro-
grammable divider.
USB 2.0 On-the-Go Dual-Role Device Controller
The USB 2.0 on-the-go (OTG) dual-role device controller pro-
vides a low-cost connectivity solution for the growing adoption
of this bus standard in industrial applications, as well as con-
sumer mobile devices such as cell phones, digital still cameras,
and MP3 players. The USB 2.0 controller allows these devices to
transfer data using a point-to-point USB connection without
the need for a PC host. The module can operate in a traditional
USB peripheral-only mode as well as the host mode presented
in the OTG supplement to the USB 2.0 specification.
The USB clock is provided through a dedicated external crystal
or crystal oscillator.
The USB OTG dual-role device controller includes a phase
locked loop with programmable multipliers to generate the nec-
essary internal clocking frequency for USB.
Housekeeping ADC (HADC)
The HADC provides a general-purpose, multichannel succes-
sive approximation analog-to-digital converter. It supports the
following features:
• 12-bit ADC core (10-bit accuracy) with built-in sample and
hold
• 4 single-ended input channels
• Throughput rates up to 1 MSPS
• Single external reference with analog inputs between 0 V
and 3.3 V
• Selectable ADC clock frequency including the ability to
program a prescaler
• Adaptable conversion type: allows single or continuous
conversion with option of autoscan
• Auto sequencing capability with up to 4 autoconversions in
a single session. Each conversion can be programmed to
select any input channel.
• Four data registers (individually addressable) to store con-
version values
System Crossbars (SCB)
The system crossbars (SCB) are the fundamental building
blocks of a switch-fabric style for (on-chip) system bus inter-
connection. The SCBs connect system bus masters to system
bus slaves, providing concurrent data transfer between multiple
bus masters and multiple bus slaves. A hierarchical model—
built from multiple SCBs—provides a power and area efficient
system interconnect, which satisfies the performance and flexi-
bility requirements of a specific system.
The SCBs provide the following features:
• Highly efficient, pipelined bus transfer protocol for sus-
tained throughput
• Full-duplex bus operation for flexibility and reduced
latency
• Concurrent bus transfer support to allow multiple bus
masters to access bus slaves simultaneously
• Protection model (privileged/secure) support for selective
bus interconnect protection
POWER AND CLOCK MANAGEMENT
The processor provides three operating modes, each with a dif-
ferent performance/power profile. Control of clocking to each
of the processor peripherals also reduces power consumption.
See Table 5 for a summary of the power settings for each mode.
System Crystal Oscillator and USB Crystal Oscillator
The processor can be clocked by an external crystal (see
Figure 4), a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator. If an external clock is used, it
should be a TTL compatible signal and must not be halted,
changed, or operated below the specified frequency during nor-
mal operation. This signal is connected to the SYS_CLKIN pin
of the processor. When an external clock is used, the SYS_XTAL
pin must be left unconnected. Alternatively, because the proces-
sor includes an on-chip oscillator circuit, an external crystal
may be used.
For fundamental frequency operation, use the circuit shown in
Figure 4. A parallel-resonant, fundamental frequency, micro-
processor grade crystal is connected across the SYS_CLKIN and
SYS_XTAL pins. The on-chip resistance between SYS_CLKIN
and the SYS_XTAL pin is in the 500 kΩ range. Further parallel
resistors are typically not recommended.
The two capacitors and the series resistor shown in Figure 4
fine-tune phase and amplitude of the sine frequency. The capac-
itor and resistor values shown in Figure 4 are typical values
only. The capacitor values are dependent upon the load capaci-
tance recommendations of the crystal manufacturer and the
PCB physical layout. The resistor value depends on the drive
Rev. A | Page 12 of 116 | September 2015

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