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DS3153 Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DS3153
Beschreibung Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 30 Seiten
DS3153 Datasheet, Funktion
DEMO KIT AVAILABLE
www.maxim-ic.com
DS3151/DS3152/DS3153/DS3154
Single/Dual/Triple/Quad
DS3/E3/STS-1 LIUs
GENERAL DESCRIPTION
The DS3151 (single), DS3152 (dual), DS3153
(triple), and DS3154 (quad) line interface units (LIUs)
perform the functions necessary for interfacing at the
physical layer to DS3, E3, or STS-1 lines. Each LIU
has independent receive and transmit paths and a
built-in jitter attenuator.
APPLICATIONS
SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSUs/DSUs
FUNCTIONAL DIAGRAM
LINE IN
DS3, E3,
OR STS-1
EACH LIU
RXP
RXN
CLK
DATA
Dallas
Semiconductor
DS315x
LINE OUT
DS3, E3,
OR STS-1
TXP
TXN
CLK
DATA
RECEIVE
CLOCK
AND DATA
CONTROL
STATUS
TRANSMIT
CLOCK
AND DATA
FEATURES
Single, Dual, Triple, or Quad Integrated
Transmitter, Receiver, and Jitter Attenuators for
DS3, E3, and STS-1
Each Port Independently Configurable
Perform Receive Clock/Data Recovery and
Transmit Waveshaping
Hardware or CPU Bus Configuration Options
Jitter Attenuators can be Placed in Either the
Receive or Transmit Paths
Interface to 75Ω Coaxial Cable at Lengths Up to
380m (DS3), 440m (E3), or 360m (STS-1)
Use 1:2 Transformers on Tx and Rx
Require Minimal External Components
Local and Remote Loopbacks
Low-Power 3.3V Operation (5V Tolerant I/O)
Industrial Temperature Range: -40°C to +85°C
Small Package: 144-Pin, 13mm x 13mm
Thermally Enhanced CSBGA
IEEE 1149.1 JTAG Support
Features continued on page 5.
ORDERING INFORMATION
PART
DS3151
DS3151N
DS3152
DS3152N
DS3153
DS3153N
DS3154
DS3154N
LIUs
1
1
2
2
3
3
4
4
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
144 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS3153 Datasheet, Funktion
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 1-A. Applicable Telecommunications Standards
SPECIFICATION
T1.102-1993
T1.107-1995
T1.231-1997
T1.404-1994
G.703
G.751
G.775
G.823
G.824
O.151
ETS 300 686
ETS 300 687
ETS EN 300 689
TBR 24
GR-253-CORE
GR-499-CORE
SPECIFICATION TITLE
ANSI
Digital Hierarchy—Electrical Interfaces
Digital Hierarchy—Formats Specification
Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring
Network-to-Customer Installation—DS3 Metallic Interface Specification
ITU-T
Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991
Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps and the
Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification, 1993
Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance
Criteria, November 1994
The Control of Jitter and Wander within Digital Networks that are Based on the 2048kbps
Hierarchy, 1993
The Control of Jitter and Wander within Digital Networks that are Based on the 1544kbps
Hierarchy, 1993
Error Performance Measuring Equipment Operating at the Primary Rate and Above,
October 1992
ETSI
Business TeleCommunications; 34Mbps and 140Mbps Digital Leased Lines (D34U,
D34S, D140U, and D140S); Network Interface Presentation, 1996
Business TeleCommunications; 34Mbps Digital Leased Lines (D34U and D34S);
Connection Characteristics, 1996
Access and Terminals (AT); 34Mbps Digital Leased Lines (D34U and D34S); Terminal
equipment interface, July 2001
Business TeleCommunications; 34Mbps Digital Unstructured and Structured Lease Lines;
Attachment Requirements for Terminal Equipment Interface, 1997
TELCORDIA
SONET Transport Systems: Common Generic Criteria, Issue 2, December 1995
Transport Systems Generic Requirements (TSGR): Common Requirements, Issue 1,
December 1998
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DS3153 pdf, datenblatt
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
Table 4-C. Receiver Pin Descriptions
NAME
RXPn,
RXNn
RCLKn
RPOSn/
RDATn
RNEGn/
RLCVn
RTSn
RLOSn
RMONn
RJAn
I/O FUNCTION
I
Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75Ω coaxial cable
through a 1:2 step-up transformer (Figure 1-1).
Receiver Clock. The recovered clock is output on the RCLK pin. Recovered data is output on the
O3
RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK (RCINV = 0) or the rising edge of
RCLK (RCINV = 1). During a loss of signal (RLOS = 0), the RCLK output signal is derived from the
LIU’s master clock.
Receiver Positive AMI/Receiver Data. When the receiver is configured to have a bipolar interface
O3
(RBIN = 0), RPOS pulses high for each positive AMI pulse received. When the receiver is
configured to have a binary interface (RBIN = 1), RDAT outputs decoded binary data. RPOS/RDAT
is updated either on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
Receiver Negative AMI/Line-Code Violation. When the receiver is configured to have a bipolar
interface (RBIN = 0), RNEG pulses high for each negative AMI pulse received. When the receiver is
O3 configured to have a binary interface (RBIN = 1), RLCV pulses high to flag code violations. See
Section 6 for further details on code violations. RNEG/RLCV is updated either on the falling edge of
RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
Receiver Tri-State Enable (Active Low). RTS tri-states the RPOS/RDAT, RNEG/RLCV, and RCLK
receiver outputs. This feature supports applications requiring LIU redundancy. Receiver outputs
I
from multiple LIUs can be wire-ORed together, eliminating the need for external switches or muxes.
The receiver continues to operate internally when RTS is low.
0 = tri-state the receiver outputs
1 = enable the receiver outputs
Receiver Loss of Signal (Active Low, Open Drain). RLOS is asserted upon detection of 175 ±75
consecutive zeros in the receive data stream. RLOS is deasserted when there are no excessive
O zero occurrences over a span of 175 ±75 clock periods. An excessive zero occurrence is defined as
three or more consecutive zeros in the DS3 and STS-1 modes or four or more zeros in the E3
mode. See Section 6 for additional details.
Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is
enabled to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This
I
feature should be enabled when the device is being used to monitor signals that have been
resistively attenuated by a monitor jack.
0 = disable the monitor preamp
1 = enable the monitor preamp
Receiver Jitter Attenuator Enable
I
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
(Note that TJA = 1 takes precedence over RJA = 1.)
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