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D75P0016 Schematic ( PDF Datasheet ) - Renesas

Teilenummer D75P0016
Beschreibung UPD75P0016
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
D75P0016 Datasheet, Funktion
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P0016
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P0016 replaces the µPD750008’s internal mask ROM with a one-time PROM and features expanded
ROM capacity.
Because the µPD75P0016 supports programming by users, it is suitable for use in prototype testing for system
development using the µPD750004, 750006, or 750008 products, and for use in small-lot production.
Detailed information about product features and specifications can be found in the following document
µPD750008 User's Manual: U10740E
FEATURES
Compatible with µPD750008
Memory capacity:
• PROM : 16384 × 8 bits
• RAM : 512 × 4 bits
Can operate in same power supply voltage as the mask ROM version µPD750008
• VDD = 2.2 to 5.5 V
Supports QTOP™ microcontroller
Remark QTOP Microcontroller is the general name for a total support service that includes imprinting, marking,
screening, and verifying one-time PROM single-chip microcontrollers offered by NEC Electronics.
ORDERING INFORMATION
Part number
µPD75P0016CU
µPD75P0016CU-A
µPD75P0016GB-3BS-MTX
µPD75P0016GB-3BS-MTX-A
Package
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
ROM (× 8 bits)
16384
16384
16384
16384
Caution On-chip pull-up resistors by mask option cannot be provided.
Remark Products with “-A” at the end of the part number are lead-free products.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U10328EJ3V3DS00 (3rd edition)
Date Published August 2005 N CP(K)
Printed in Japan
The mark shows major revised points.






D75P0016 Datasheet, Funktion
µPD75P0016
2. BLOCK DIAGRAM
BASIC INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
TI0/P13
PTO0/P20
8-BIT
TIMER/EVENT
COUNTER #0
INTT0
TOUT0
PTO1/P21
8-BIT TIMER
COUNTER
#1
INTT1
SI/SB1/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
INTCSI
TOUT0
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60-
KR7/P73
8
INTERRUPT
CONTROL
BUZ/P23
WATCH
TIMER
INTW
PROGRAM
COUNTER (14)
PROGRAM
MEMORY
(PROM)
16384 × 8 BITS
SP (8)
CY
ALU SBS
BANK
GENERAL
REGISTER
DECODE
AND
CONTROL
DATA
MEMORY
(RAM)
512 × 4 BITS
fx/2N
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
CPU CLOCK
Φ
SYSTEM CLOCK
GENERATOR
SUB
MAIN
STAND BY
CONTROL
PCL/P22
XT1XT2 X1 X2
VPP VDD VSS RESET
BIT SEQ.
BUFFER (16)
PORT0 4 P00-P03
PORT1 4 P10-P13
PORT2 4 P20-P23
PORT3 4 P30/MD0-P33/MD3
PORT4 4 P40/D0-P43/D3
PORT5 4 P50/D4-P53/D7
PORT6 4 P60-P63
PORT7 4 P70-P73
PORT8 2 P80, P81
6 Data Sheet U10328EJ3V3DS

6 Page









D75P0016 pdf, datenblatt
µPD75P0016
4. SWITCHING BETWEEN MK I AND MK II MODES
Setting a stack bank selection (SBS) register for the µPD75P0016 enables the program memory to be switched
between the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750004, 750006, or 750008
using the µPD75P0016.
When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of µPD750004, 750006, and 750008)
When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750004, 750006, and 750008)
4.1 Differences between Mk I Mode and Mk II Mode
Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the µPD75P0016.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item
Program counter
Program memory (bytes)
Data memory (bits)
Stack
Stack bank
Stack bytes
Instruction
BRA !addr1
CALLA !addr1
Instruction CALL !addr
execution time CALLF !faddr
Supported mask ROM versions and
mode
Mk I mode
PC13-0
16384
512 × 4
Selectable from memory banks 0 and 1
2 bytes
None
3 bytes
Provided
Mk II mode
3 machine cycles
2 machine cycles
Mk I mode of µPD750004, 750006, and
750008
4 machine cycles
3 machine cycles
Mk II mode of µPD750004, 750006, and
750008
Caution
The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when
a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.
Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
12 Data Sheet U10328EJ3V3DS

12 Page





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