Datenblatt-pdf.com


CLC949 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC949
Beschreibung Very Low-Power/ 12-Bit/ 20MSPS Monolithic A/D Convertter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 12 Seiten
CLC949 Datasheet, Funktion
August 1996
N
Comlinear CLC949
Very Low-Power, 12-Bit,
20MSPS Monolithic A/D Convertter
General Description
The Comlinear CLC949 is a 12-bit analog-to-digital converter sub-
system including 12-bit quantizer, sample-and-hold amplifier, and
internal reference. The CLC949 has been optimized for low power
operation with high dynamic range. The CLC949 has a unique
feature which allows the user to adjust internal bias levels in the
converter which results in a trade-off between power dissipation
and maximum conversion rate. With bias set for 220mW power
dissipation the converter operates at 20MSPS. Under these
conditions, dynamic performance with a 9.9MHz analog input is
typically 68dB SNR and 72dBc SFDR. When bias is set for only
65mW power dissipation the converter maintains excellent perfor-
mance at 5MSPS. With a 2.4MHz analog input signal the SNR is
70dB and SFDR is 78dBc. This excellent dynamic performance in
the frequency domain without high power requirements make the
part a strong performer for communications and radar applications.
The low input noise of the CLC949, its 0.5LSB differential linearity
error specification, fast settling, and low power dissipation also
lead to excellent performance in imaging systems. All parts are
thoroughly tested to insure that guaranteed specifications are met.
The CLC949 incorporates an input sample-and-hold amplifier
followed by a quantizer which uses a pipelined architecture to min-
imize comparator count and the associated power dissipation
penalty. An on-board voltage reference is provided. Analog input
signals, conversion clock, and a single supply are all that are
required for CLC949 operation.
Features
s Very low/programmable power
0.07W @ 5MSPS
0.22W @ 20MSPS
0.40W @ 30MSPS
s Single supply operation (+5V)
s 0.5 LSB differential linearity error
s Wide dynamic range
72dBc spurious-free dynamic range
68dB signal-to-noise ratio
s No missing codes
Applications
s CCD imaging
s IR imaging
s FLIR processing
s Medical imaging
s High definition video
s Instrumentation
s Radar processing
s Digital communications
The CLC949 exhibits very stable performance over the commercial
and industrial temperature ranges. Most parameters shift very
little as the ambient temperature changes from -40°C to 85°C. An
exception to this rule is the dynamic performance of the converter.
As the temperature is increased, the distortion increases,
especially at higher input frequencies. This can be seen in the plot
on page 3. For input frequencies below 7MHz, there is relatively
little variation in distortion as the temperature is changed, but at
higher input frequencies, it is apparent that the performance
degrades as the temperature is increased.
SFDR (dBc)
Note that the reason for this degradation is the reduced ability of
the CLC949 to handle high slew rates at high temperatures. In
applications such as CCD imaging systems, where the slew rate at
the A/D sampling instant is very low, this degradation will not be
nearly so pronounced.
For applications requiring high temperature operation and very low
distortion with high frequency input signals, use of an external
sample-and-hold amplifier may enhance performance by reducing
the slew rates that the CLC949 sees during its sampling period (just
after the falling edge of CLK).
The CLC949 is fabricated in a 0.9µm CMOS technology. The
CLC949ACQ is specified over the commercial temperature range
of 0°C to +70°C and the CLC949AJQ is specified over the indus-
trial range of -40°C to +85°C. Both are packaged in a 44-pin
Plastic Leaded Chip Carrier (PLCC).
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
Power Dissipation vs. Conversion Rate
200
150
100
50
0
0 5 10 15 20
Sample Rate (MSPS)
http://www.national.com






CLC949 Datasheet, Funktion
VIN
50
VINP
15pF
CLC949
VREFMO
VINN
TM01-1T 15pF
Figure 3: Transformer Coupled Input
Since the transformer response does not extend to DC it
is not an effective solution for applications which require
DC coupled inputs.
To drive the input of the CLC949, and retain DC
information, an amplifier configuration is required.
Comlinear suggests the use of the circuit shown in Figure 4.
This circuit is used on the E949PCASM.
500
VIN
R29
400
R30
50
R7
400
1k
-
CLC428
+ U5A
1k
-
CLC428
+ U5B
1.25k
+5V
500
500+5V
-
CLC409
+ U7
R3
400
R27
+5V 50
R10
50
R8
+
R2
400
50CLC409
R26
- U6
50
15pF
15pF
VREFMO
VINP
CLC949
VINN
400
Figure 4: Amplifier Coupled Input
In this circuit U7 buffers the analog input with a gain of
+1, and U6 buffers the input with a gain of -1. The
circuit has been designed so that U6 and U7 have the
same loop gain, thereby offering the best possible match
of their AC characteristics. U5 is used to generate the
required offset voltages which are summed into the input
signal via U6 and U7. The CLC409 was selected for U6
and U7 due to its current feedback topology which allows
for very low distortion even at high frequencies, and its
excellent phase linearity. Phase match between U6 and
U7 is critical for good pulse response. To generate the
D.C. offsets, the CLC428 dual Op-amp was selected.
The CLC428 is a voltage-feedback op amp with very
good DC characteristics, and the large bandwidth makes
the output impedance low over a wide range of frequen-
cies, allowing good AC performance.
Regardless of how the input is driven, a small capacitor
(15pF) should be added from the VINP and VINN
terminals to GND. This will help to reduce the current
transients that are generated by the CLC949 inputs
during sampling.
Reference Generation
The CLC949 has internally generated reference
voltages. To use these references, you must externally
connect the reference inputs by shorting VREFPO to
VREFP and VREFNO to VREFN. During the conversion
cycle, the impedance on these four pins varies
dynamically. To maintain stable biases on these pins you
must bypass them with 0.1µF to GND. If you want to pro-
vide an external reference, then you have to be careful
to provide low output impedance drivers to the VREFP and
VREFN pins. Bypass capacitors on all reference pins are
recommended for best performance.
Bias Control
One of the unique features of the CLC949 is that it allows
you to set the internal bias current of the device. When
designing an A/D converter a tradeoff is made between
the amount of power dissipated and the
performance. The CLC949 allows you to make this
tradeoff yourself. The bias current is controlled by the
pins BC0 and BC1. These two pins are digital input pins
from which one of three discrete bias points may be
selected (see truth table on page 4 of this datasheet) or
an external bias may be provided through the analog bias
control pin BIASC. If BC0 and BC1 are left open, they
will drift low and provide the default bias condition which
results in 220mW of dissipation at 20MHz sampling rate.
The actual power dissipated by the device is a function
of both the bias condition and the sample rate. The
relationship between power and speed is shown for the
three discrete bias points in Figure 5.
Power Dissipation vs. Sample Rate
400
High Bias
300
200
Medium Bias
100
Low Bias
0
100k
1M 10M
Sample Rate (Hz)
40M
Figure 5: Power Dissipation vs. Sample Rate
As the bias is turned up, the ability of the CLC949 to
handle high frequency inputs and the power dissipation
of the CLC949 increases. To use the BIASC pin, attach
a resistor from the pin to VDDA. The current drawn by this
resistor is mirrored in the device to set the internal bias
currents. A smaller value resistor will result in higher bias
currents and higher performance.Beyond a certain
point, additional improvement is not seen, although
power continues to increase. For this reason, it is
recommended that bias setting resistors of less than
10K not be used. To generate the graph in Figure 6 a
CLC949 was set to sample a signal 1dB below full scale
http://www.national.com
6

6 Page









CLC949 pdf, datenblatt
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval
of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
National Semiconductor
Europe
Fax: (+49) 0-180-530 85 86
E-mail: europe.support.nsc.com
Deutsch Tel: (+49) 0-180-530 85 85
English Tel: (+49) 0-180-532 78 32
Francais Tel: (+49) 0-180-532 93 58
Italiano Tel: (+49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block
Ocean Centre, 5 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
http://www.national.com
12
Lit #150949-004

12 Page





SeitenGesamt 12 Seiten
PDF Download[ CLC949 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CLC949Very Low-Power/ 12-Bit/ 20MSPS Monolithic A/D ConvertterNational Semiconductor
National Semiconductor
CLC949CLC949 Very Low Power 12-Bit 20 MSPS Monolithic A/D Converter (Rev. A)Texas Instruments
Texas Instruments
CLC949ACQVery Low-Power/ 12-Bit/ 20MSPS Monolithic A/D ConvertterNational Semiconductor
National Semiconductor
CLC949AJQVery Low-Power/ 12-Bit/ 20MSPS Monolithic A/D ConvertterNational Semiconductor
National Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche