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CLC5957 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC5957
Beschreibung 12-bit/ 70MSPS Broadband Monolithic A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 12 Seiten
CLC5957 Datasheet, Funktion
N
October 1999
CLC5957
12-bit, 70MSPS Broadband Monolithic A/D Converter
General Description
The CLC5957 is a monolithic 12-bit, 70MSPS analog-to-digital
converter. The device has been optimized for use in IF-sampled
digital receivers and other applications where high resolution,
high sampling rate, wide dynamic range, low power dissipation,
and compact size are required. The CLC5957 features differential
analog inputs, low jitter differential universal clock inputs, a low
distortion track-and-hold with 0-300MHz input bandwidth, a band-
gap voltage reference, data valid clock output, TTL compatible
CMOS (3.3V or 2.5V) programmable output logic, and a propri-
etary 12-bit multi-stage quantizer. The CLC5957 is fabricated on
the ABIC-V 0.8 micron BiCMOS process.
The CLC5957 features a 74dBc spurious free dynamic range
(SFDR) and a 67dB signal to noise ratio (SNR). The wideband
track-and-hold allows sampling of IF signals to greater than
250MHz. The part produces two-tone, dithered, SFDR of 83dBFS
at 75MHz input frequency. The differential analog input provides
excellent common mode rejection, while the differential universal
clock inputs minimize jitter. The 48-pin TSSOP package provides
an extremely small footprint for applications where space is a
critical consideration. The CLC5957 operates from a single +5V
power supply. Operation over the industrial temperature range of
-40°C to +85°C is guaranteed. National Semiconductor tests
each part to verify compliance with the guaranteed specifications.
Features
• 70MSPS
• Wide dynamic range
SFDR: 74dBc
SFDR w/dither: 85dBFS
SNR: 67dB
• IF sampling capability
• Input bandwidth = 0-300MHz
• Low power dissipation: 640mW
• Very small package: 48-pin TSSOP
• Single +5V supply
• Data valid clock output
• Programmable output levels:
3.3V or 2.5V
Applications
• Cellular base-stations
• Digital communications
• Infrared/CCD imaging
• IF sampling
• Electro-optics
• Instrumentation
• Medical imaging
• High definition video
ME79TG
N CL5C9559657
IMMTTDD
Actual Size
Clock
In
AIn T/H
ADC Block Diagram
DAV
3-bit
Q
3
3-bit
Q
3-bit
Q
33
Bit Align/Error Correct
3-bit
Q
3
12
ADC
Out
First IF Receiver
IF
Input
IF
Saw
~~
BPF
(150MHz
typ.)
DVGA
(G = 42dB)
Noise
BPF
3-bit (Gain Control)
CLC5957
12-bit
70MSPS
ADC
CLC5902
12
DAV
Dig.
Tuner/
Filter
AGC
20
Decimation/filter = 190/0.8
Output BW = 50M/190 X 0.8 = 210KHz
Single Tone Output Spectrum w/Dither
0
-10
Fin = 25.3MHZ
Fsample = 66MHz
-20
-30
-40
-50
-60
-70
-80
-90
-100
0 4 8 12 16 20 24 28 32
Frequency (MHz)
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
Receiver SINAD vs. Input Amplitude
90
80
70
60
50
40
30
20
10
0
-125 -100
-75
-50
-25
Input (dBFS)
0
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CLC5957 Datasheet, Funktion
GND 1
GND 2
GND 3
GND 4
+AVCC 5
+AVCC 6
+AVCC 7
GND 8
ENCODE 9
ENCODE 10
GND 11
GND 12
AIN 13
AIN 14
GND 15
+AVCC 16
+AVCC 17
+AVCC 18
GND 19
GND 20
VCM 21
+AVCC 22
GND 23
GND 24
CLC5957
Physical Dimensions
Symbol
A
A1
A2
b
b1
c
c1
D
E
E1
e
L
L1
R1
Min Max
– 1.10
0.05 0.15
0.80 1.05
0.17 0.27
0.17 0.23
0.09 0.20
0.09 0.16
12.40 12.60
8.1 BSC
6.00 6.20
0.50 BSC
0.50 0.75
1.00 REF
0.127
Notes
2
2
Notes:
1. All dimensions are in millimeters.
2. Dimensions D and E1 do not include mold protrusion.
Allowable protrusion is 0.20mm per side.
CLC5957 Pin Definitions
48 GND
47 GND
46 +DVCC
45 D11 (MSB)
44 D10
43 D9
42 D8
41 D7
40 D6
39 D5
38 +DVCC
37 +DVCC
36 GND
35 GND
34 D4
33 D3
32 D2
31 D1
30 D0 (LSB)
29 GND
28 OUTLEV
27 DAV
26 GND
25 GND
AIN, AIN
ENCODE,
ENCODE
D0-D11
DAV
OUTLEV
VCM
GND
+AVCC
+DVCC
(Pin 13, 14) Differential input with a common mode voltage
of +2.4V. The ADC full scale input is 1.024Vpp on each of
the complimentary input signals.
(Pin 9, 10) Differential clock where ENCODE initiates a new
data conversion cycle on each rising edge. Logic for these
inputs are 50% duty cycle universal differential signal
(>200mV). The clock input is internally biased to VCC/2 with
a termination impedance of 2.5k.
(Pins 30-34, 39-45) Digital data outputs are CMOS and
TTL compatible. D0 is the LSB and D11 is the MSB. MSB
is inverted. Output coding is two’s complement.
(Pin 27) Data Valid Clock. Data is valid on rising edge.
(Pin 28) Output Logic 3.3V or 2.5V option.
Open = 3.3V, GND = 2.5V.
(Pin 21) Internal common mode voltage reference.
Nominally +2.4V. Can be used for the input common
mode voltage. This voltage is derived from an internal
bandgap reference.
(Pins 1-4, 8, 11, 12, 15, 19, 20, 23-26, 29, 35, 36, 47, 48)
circuit ground.
(Pins 5-7, 16-18, 22,) +5V power supply for the analog
section. Bypass to ground with a 0.1µF capacitor.
(Pin 37, 38, 46) +5V power supply for the digital section.
Bypass to ground with a 0.1µF capacitor.
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CLC5957 pdf, datenblatt
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of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
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