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PDF CLC5632IMX Data sheet ( Hoja de datos )
| Número de pieza | CLC5632IMX | |
| Descripción | Dual/ High Output/ Programmable Gain Buffer | |
| Fabricantes | National Semiconductor | |
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CLC5632
Dual, High Output, Programmable Gain Buffer
June 1999
General Description
The CLC5632 is a dual, low-cost, high-speed (130MHz) buffer
which features user-programmable gains of +2, +1, and -1V/V.
The CLC5632 also has a new output stage that delivers high
output drive current (130mA), but consumes minimal quiescent
supply current (3.0mA/ch) from a single 5V supply. Its current
feedback architecture, fabricated in an advanced complementary
bipolar process, maintains consistent performance over a wide
range of gains and signal levels, and has a linear-phase response
up to one half of the -3dB frequency.
The CLC5632 offers 0.1dB gain flatness to 30MHz and differen-
tial gain and phase errors of 0.08% and 0.02°. These features are
ideal for professional and consumer video applications.
The CLC5632 offers superior dynamic performance with a
130MHz small-signal bandwidth, 410V/µs slew rate and 5.0ns
rise/fall times (2Vstep). The combination of low quiescent power,
high output current drive, and high-speed performance make
the CLC5632 well suited for many battery-powered personal
communication/computing systems.
The ability to drive low-impedance, highly capacitive loads,
makes the CLC5632 ideal for single ended cable applications.
It also drives low impedance loads with minimum distortion.
The CLC5632 will drive a 100Ω load with only -82/-69dBc
second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz).
With a 25Ω load, and the same conditions, it produces only -71/
-73dBc second/third harmonic distortion. It is also optimized for
driving high currents into single-ended transformers and coils.
When driving the input of high-resolution A/D converters, the
CLC5632 provides excellent -86/-96dBc second/third harmonic
distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast
settling time.
Features
s 130mA output current
s 0.08%, 0.02° differential gain, phase
s 3.0mA/ch supply current
s 130MHz bandwidth (Av = +2)
s -86/-96dBc HD2/HD3 (1MHz)
s 17ns settling to 0.05%
s 410V/µs slew rate
s Stable for capacitive loads up to 1000pf
s Single 5V to ±5V supplies
Applications
s Video line driver
s Coaxial cable driver
s Twisted pair driver
s Transformer/coil driver
s High capacitive load driver
s Portable/battery-powered applications
s A/D driver
Maximum Output Voltage vs. RL
10
9
8
7 VCC = ±5V
6
5
4
3 Vs = +5V
2
1
10 100
RL (Ω)
1000
Typical Application
Differential Line Driver with Load Impedance Conversion
Vd/2
Vin
Rt
1
1kΩ
2 1kΩ -
+
8
7
3 1kΩ 1kΩ 6
45
CLC5632
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
Rm/2
Req
1:n
Rm/2
-Vd/2
Zo
UTP
Io
RL
+
Vo
-
Rt2
Note: Supplies and bypassing not shown.
OUT1
-IN1
+IN1
-VCC
Pinout
DIP & SOIC
1kΩ
1kΩ -
+
1kΩ 1kΩ
+VCC
OUT2
-IN2
+IN2
http://www.national.com
1 page  
±5V Typical Performance (Av = +2, RL = 100Ω, VCC = ± 5V, unless specified)
Frequency Response
Vo = 1.0Vpp
Gain
Av = -1
Av = +1
Phase
Av = +2
1M 10M 100M
Frequency (Hz)
Frequency Response vs. Vo (Av = 2)
0
-45
-90
-135
-180
-225
Vo = 0.1Vpp
Frequency Response vs. RL
Vo = 1.0Vpp
Gain
RL = 1kΩ
Phase
RL = 100Ω
RL = 25Ω
1M 10M 100M
Frequency (Hz)
0
-90
-180
-270
-360
-450
Frequency Response vs. Vo (Av = 1)
Vo = 1Vpp
Vo = 0.1Vpp
Vo = 5Vpp
Vo = 1Vpp
Vo = 5Vpp
Vo = 2Vpp
Vo = 2Vpp
Gain Flatness & Linear Phase
Gain
0.4
0.3
0.2
Phase
0.1
0
-0.1
0 5 10 15 20 25 30
Frequency (MHz)
Frequency Response vs. Vo (Av = -1)
Vo = 1Vpp
Vo = 5Vpp
Vo = 0.1Vpp
Vo = 2Vpp
1M 10M 100M
Frequency (Hz)
Large & Small Signal Pulse Response
Large Signal
Small Signal
Time (20ns/div)
2nd & 3rd Harmonic Distortion, RL = 25Ω
-40
3rd, 10MHz
-50
2nd, 10MHz
-60
-70 2nd, 1MHz
3rd, 1MHz
-80
-90
0
1 2 34
Output Amplitude (Vpp)
Short Term Settling Time
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
1
10 100 1000
Time (ns)
5
10000
1M 10M 100M
Frequency (Hz)
Differential Gain & Phase
-0.025
Gain Pos Sync
-0.050
0.1
0.05
-0.075 Phase Pos Sync
0
-0.100
-0.125
Phase Neg Sync
Gain Neg Sync
-0.05
-0.1
-0.150
1
23
Number of 150 Ω Loads
-0.15
4
2nd & 3rd Harmonic Distortion, RL = 100Ω
-55
-60 3rd, 10MHz
-65
-70
2nd, 10MHz
-75
-80
2nd, 1MHz
-85
-90 3rd, 1MHz
-95
0
0.5 1 1.5 2
Output Amplitude (Vpp)
2.5
Long Term Settling Time
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
1µ
10µ 100µ 1m
Time (s)
10m 100m
5
1M 10M 100M
Frequency (Hz)
2nd & 3rd Harmonic Distortion vs. Frequency
-50
Vo = 2Vpp
-60
-70
2nd
RL = 100Ω
-80
2nd
RL = 1kΩ
-90
-100
1
3rd
RL = 1kΩ
3rd
RL = 100Ω
Frequency (MHz)
10
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-50
-60
-70 3rd, 10MHz
2nd, 10MHz
-80
-90 2nd, 1MHz
-100 3rd, 1MHz
-110
0
1 2 34
Output Amplitude (Vpp)
IBN & VOS vs. Temperature
4.0
5
3.0
3.8
3.6
3.4
3.2
3.0
2.8
-60
VOS
IBN
-20 20 60 100
Temperature (°C)
2.5
2.0
1.5
1.0
0.5
0
140
http://www.national.com
5 Page 
Vd/2
Vin
Rt
1
1kΩ
2 1kΩ -
+
8
7
3 1kΩ 1kΩ 6
45
CLC5632
Rm/2
Req
1:n
Rm/2
-Vd/2
Zo
UTP
Io
RL
Rt2
Note: Supplies and bypassing not shown.
Select the transformer so that it loads the line with a
value very near Zo over frequency range. The output
impedance of the CLC5632 also affects the match. With
an ideal transformer we obtain:
Return Loss = −20 ⋅ log10
n2 ⋅ Zo(5632)(jω)
Zo
, dB
Figure 16: Differential Line Driver with
Load Impedance Conversion
Set up the CLC5632 as a difference amplifier:
s Set the Channel 1 amplifier to a gain of +1V/V
s Set the Channel 2 amplifier to a gain of -1V/V
Make the best use of the CLC5632’s output drive
capability as follows:
Rm
+ Req
=
2 ⋅ Vmax
Imax
where Req is the transformed value of the load imped-
ance, Vmax is the Output Voltage Range, and Imax is the
maximum Output Current.
Match the line’s characteristic impedance:
RL = Zo
Rm = Req
n = RL
Req
where Zo(5632)(jω) is the output impedance of the
CLC5632 and |Zo(5632)(jω)| << Rm.
The load voltage and current will fall in the ranges:
Vo ≤ n ⋅ Vmax
Io
≤ Imax
n
The CLC5632’s high output drive current and low
distortion make it a good choice for this application.
Differential Input/Differential Output Amplifier
Figure 17 below illustrates a differential input/differential
output configuration. The bypass capacitors are the only
Vin2
CLC5632
1kΩ 1kΩ
0.1µF
6.8µF
-5V
Vout2
Vin1
6.8µF 0.1µF
+5V
1kΩ 1kΩ
Vout1
Vout1 – Vout2 = (Vin1 – Vin2) x 2
external components required.
Figure 17: Differential Input/Differential
Output Amplifier
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11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CLC5632IMX.PDF ] | |
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