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CLC5523IMX Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC5523IMX
Beschreibung Low-Power/ Variable Gain Amplifier
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 12 Seiten
CLC5523IMX Datasheet, Funktion
March 2000
CLC5523
Low-Power, Variable Gain Amplifier
General Descriptions
The CLC5523 is a low power, wideband, DC-coupled, voltage-
controlled gain amplifier. It provides a voltage-controlled gain
block coupled with a current feedback output amplifier. High
impedance inputs and minimum dependence of bandwidth on
gain make the CLC5523 easy to use in a wide range of
applications. This amplifier is suitable as a continuous gain
control element in a variety of electronic systems which benefit
from a wide bandwidth of 250MHz and high slew rate of
1800V/ms, with only 135mW of power dissipation.
Input impedances in the megaohm range on both the signal
and gain control inputs simplify driving the CLC5523 in any
application. The CLC5523 can be configured to use pin 3 as a
low impedance input making it an ideal interface for current
inputs. By using the CLC5523’s inverting configuration in which
RG is driven directly, inputs which exceed the device’s input
voltage range may be used.
The gain control input (VG), with a 0 to 2V input range, and a
linear-in-dB gain control, simplifies the implementation of AGC
circuits. The gain control circuit can adjust the gain as fast as
4dB/ns. Maximum gains from 2 to 100 are accurately and simply
set by two external resistors while attenuation of up to 80dB from
this gain can be achieved.
The extremely high slew rate of 1800V/ms and wide bandwidth
provides high speed rise and fall times of 2.0ns, with settling time
for a 2 volt step of only 22ns to 0.2%. In time domain applications
where linear phase is important with gain adjust, the internal cur-
rent mode circuitry maintains low deviation of delay over a wide
gain adjust range.
Features
s Low power: 135mW
s 250MHz, -3dB bandwidth
s Slew rate 1800V/ms
s Gain flatness 0.2dB @ 75MHz
s Rise & fall times 2.0ns
s Low input voltage noise 4nV/ÖHz
Applications
s Automatic gain control
s Voltage controlled filters
s Automatic signal leveling for A/D
s Amplitude modulation
s Variable gain transimpedance
Frequency Response with Changes in Vg
30
20
10
0
-10
-20
-30
-40
-50
1M
10M 100M
Frequency (Hz)
Typical Application
Variable Gain Amplifier
Circuit
Vin
Rg
VG
+5V
2
1
+
8
CLC5523 6
3-
4
7
5 Rf
25W -5V
Vo
RL
Pinout
DIP & SOIC
VG
VIN
Rg
GND
X1
-
+
+VCC
I-
VO
-VCC
© 2000 National Semiconductor Corporation
Printed in the U.S.A.
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CLC5523IMX Datasheet, Funktion
The CLC425 is a low noise wideband voltage feedback
amplifier. Setting R2 at 909W and R1 at 100W produces
a gain of 20dB. Setting Rf at 1000W as recommended
and Rg at 50W, produces a gain of 26dB in the CLC5523.
The total gain of this circuit is therefore approximately
46dB. It is important to understand that when partitioning
to obtain high levels of gain, very small signal levels will
drive the amplifiers to full scale output. For example, with
46dB of gain, a 20mV signal at the input will drive the out-
put of the CLC425 to 200mV, the output of the CLC5523
to 4V. Accordingly, the designer must carefully consider
the contributions of each stage to the overall characteris-
tics. Through gain partitioning the designer is provided
with an opportunity to optimize the frequency response,
noise, distortion, settling time, and loading effects
of each amplifier to achieve improved overall
performance.
CLC5523 Gain Control Range and Minimum Gain
Before discussing Gain Control Range, it is important to
understand the issues which limit it. The minimum gain of
the CLC5523, theoretically, is zero, but in practical circuits
is limited by the amount of feedthrough, here defined as
the difference in output levels when VG = 2V and when
VG = 0V. Capacitive coupling through the board and
package as well as coupling through the supplies will
determine the amount of feedthrough. Even at DC, the
input signal will not be completely rejected. At high fre-
quencies feedthrough will get worse because of its capac-
itive nature. At low frequencies, the feedthrough will be
80dB below the maximum gain, and therefore it can be said
that the CLC5523 has an 80dB Gain Control Range.
CLC5523 Gain Control Function
In the two plots, Gain vs. VG, we can see the gain as a
function of the control voltage. The first plot, sometimes
referred to as the S-curve, is the linear (V/V ) gain. This
is a hyperbolic tangent relationship. The second gain
curve plots the gain in dB and is linear over a wide range
of gains. Because of this, the CLC5523 gain control is
referred to as “linear-in-dB.”
For applications where the CLC5523 will be used at the
heart of a closed loop AGC circuit, the S-curve control
characteristic provides a broad linear (in dB) control
range with soft limiting at the highest gains where large
changes in control voltage result in small changes in
gain. For applications, requiring a fully linear (in dB)
control characteristic, use the CLC5523 at half gain and
below (VG ² 1V).
Avoiding Overdrive of the CLC5523
Gain Control Input
There is an additional requirement for the CLC5523 Gain
Control Input (VG): VG must not exceed +2.5V. The gain
control circuitry may saturate and the gain may actually
be reduced. In applications where VG is being driven
from a DAC, this can easily be addressed in the software.
If there is a linear loop driving VG, such as an AGC loop,
other methods of limiting the input voltage should be
implemented. One simple solution is to place a 2:1
resistive divider on the VG input. If the device driving this
divider is operating off of ±5V supplies as well, its output
will not exceed 5V and through the divider VG can not
exceed 2.5V.
Improving the CLC5523 Large Signal Performance
Figure 2 illustrates an inverting gain scheme for the
CLC5523.
VG
21
25W Vin
CLC5523 6
37
Rg 4
Rf
25W
Vo
Figure 2: Inverting the CLC5523
The input signal is applied through the Rg resistor. The
Vin pin should be grounded through a 25W resistor. The
maximum gain range of this configuration is given in the
following equation:
Avmax =
-
æ
èç
Rf
Rg
ö
ø÷
The inverting slew rate of the CLC5523 is much higher
than that of the non-inverting slew rate. This 2.5X
performance improvement comes about because in the
non-inverting configuration, the slew rate of the overall
amplifier is limited by the input buffer. In the inverting
circuit, the input buffer remains at a fixed voltage and
does not affect slew rate.
Transmission Line Matching
One method for matching the characteristic impedance of
a transmission line is to place the appropriate resistor at
the input or output of the amplifier. Figure 3 shows a typ-
ical circuit configuration for matching transmission lines.
Signal + Rs
Input -
Zo
Ri
Rg
VG
21
CLC5523 6
37
4 Rf
25W
Co
Zo Output
Ro RT
Figure 3: Transmission Line Matching
The resistors Rs, Ri, Ro, and RT are equal to the
characteristic impedance, Zo, of the transmission line or
cable. Use Co to match the output transmission line over
a greater frequency range. It compensates for the
increase of the op amp’s output impedance with frequency.
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CLC5523IMX pdf, datenblatt
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