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CLC533A8L-2A Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC533A8L-2A
Beschreibung High-Speed 4:1 Analog Multiplexer
Hersteller National Semiconductor
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Gesamt 9 Seiten
CLC533A8L-2A Datasheet, Funktion
N
CLC533
High-Speed 4:1 Analog Multiplexer
June 1999
General Description
The CLC533 is a high-speed 4:1 multiplexer employing active
input and output stages. The CLC533 also employs a closed-loop
design which dramatically improves accuracy over conventional
analog multiplexer circuits. This monolithic device is constructed
using an advanced high-performance bipolar process.
The CLC533 has been specifically designed to provide a 24ns
settling time to 0.01%. This coupled with the adjustable band-
width, makes the CLC533 an ideal choice for infrared and CCD
imaging systems, with channel-to-channel isolation of 80dB @
10MHz. Low distortion and spurious signal levels (-80dBc) make
the CLC533 a very suitable choice for I/Q processors in radar
receivers.
The CLC533 is offered over both the industrial and military tem-
perature ranges. The industrial versions, CLC533AJP\AJE\AIB,
are specified from -40°C to +85°C and are packaged in 16-pin
plastic DIPs, SOIC’s and CERDIP packages. The extended tem-
perature versions, CLC533A8B/A8L-2A, are specified from -55°C
to +125°C and are packaged in 16-pin CERDIP and 20-terminal
LCC packages.
Ordering Information ...
CLC533AJP
-40°C to +85°C 16-pin plastic DIP
CLC533AJE
-40°C to +85°C 16-pin plastic SOIC
CLC533ALC
-40°C to +85°C
dice
CLC533A8B
-55°C to +125°C 16-pin CERDIP,
MIL-STD-883
CLC533AMC
-40°C to +85°C
dice, MIL-STD-833
CLC533A8L-2A -55°C to +125°C 20-terminal LCC,
MIL-STD-883
Contact factory for other packages and DESC SMD number.
Features
s 12-bit settling (0.01%) – 17ns
s Low noise – 42µVrms
s Isolation – 80dB @ 10MHz
s 110MHz -3dB bandwidth (Av = +2)
s Low distortion – 80dB @ 5MHz
s Adjustable bandwidth – 180MHz (max)
Applications
s Infrared system multiplexing
s CCD sensor signals
s Radar I/Q switching
s High definition video HDTV
s Test and calibration
87654
GND 9
IND 10
NC 11
Vee 12
A1 13
14 15 16 17 18
3 INA
2 GND
1 NC
20 OUTPUT
19 COMP1
Functional Diagram
A1 A0
00
01
10
11
OUT
A
B
C
D
ECL Mode - DREF = open
TTL Mode - DREF = +5V
Pinout
DIP & SOIC
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com






CLC533A8L-2A Datasheet, Funktion
above 1/2 the sampling frequency will be aliased into
the baseband and will corrupt the signal of interest.
When the CLC533 is switched from one channel to
another, the output slews rapidly until it arrives at
the new signal. This high slew rate signal can capac-
itively couple into other nodes in the circuit and can
have a detrimental effect on overall performance.
Since coupling through stray capacitance and
inductances decreases with decreasing dV/dt, the
slew rate should be minimized consistent with system
throughput requirements.
be isolated from the CLC533 output via a series resistor.
The recommended series resistor Rs, for various
capacitive loads CL, can be found by referring to the
“Recommended Compensation Cap vs. Load” plot in the
“Typical Performance” section.
5050
81
130
Figure 1: ECL Level Channel SELECT Configuration
Figure 2: TTL/CMOS Level Channel
SELECT Configuration
Output Load
The final frequency response that is realized is a result of
both the compensation capacitor and the load that the
CLC533 is driving. Figure 3 below shows the effect that
CCOMP has on bandwidth for a fixed load. Graphs on the
preceding pages demonstrate the effect of CCOMP on
pulse response and settling time, and the optimum value
of CCOMP to maximize bandwidth for various amounts of
resistive loading. Because there are so many factors that
go into determining the optimum value of CCOMP it is
recommended that once a value is selected, the
application circuit be built up and larger and smaller
compensation capacitors be tried to determine the best
value for that particular circuit.
The output load that the CLC533 is driving has an effect
on the harmonic distortion of the device as well as
frequency response. Distortion is minimized with a 500
load. When driving components with a high input
impedance, addition of a load resistor can improve the
performance. If the load is capacitive in nature, it should
Small Signal Bandwidth (30MHz/div)
Figure 3
Power Supplies and Grounding
In any circuit there are connections between
components that are not desired. Some of the most com-
mon of these are the connections made through the
power supply and grounding network. The goal in laying
out the power and ground network for a mixed mode
circuit is to minimize the impedance from the power pins
to the supply, and minimize the impedance of the ground
network.
To minimize impedance of the ground and power nets,
use the heaviest possible traces and ground planes for
minimizing the DC impedance. To further reduce the
supply impedance at higher frequencies, a 6 to 10µF
capacitor should be placed between supply lines and
ground. At very high frequencies, the inductance in the
traces becomes significant and 0.01 to 0.1µF bypass
capacitors need to be placed as close to each power pin
as is practical. To reduce the negative effects of ground
impedances that will exist, consider the paths that ground
currents must take to get from the various devices on the
circuit card to the power supply. To achieve good system
performance, it is vital that large currents and high-speed
time varying currents like CMOS signals, be kept away
from precision analog components. This can be achieved
through layout of the power and ground nets. Using a
ground plane split between analog and digital sections of
the circuit forces all of the ground current from the digital
circuits to go directly to the power connector without
straying to the analog side of the card.
Optimizing for Channel-to-Channel Isolation
Although the CLC533 has excellent channel-to-
channel isolation, if there is cross talk between the input
signals before they reach the CLC533, the
multiplexer will faithfully pass these corrupted signals
through to its output and dutifully take the blame for poor
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