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CLC532AJP Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC532AJP
Beschreibung High-Speed 2:1 Analog Multiplexer
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 12 Seiten
CLC532AJP Datasheet, Funktion
N
CLC532
High-Speed 2:1 Analog Multiplexer
June 1999
General Description
The CLC532 is a high-speed 2:1 multiplexer with active input and
output stages. The CLC532 also employs a closed-loop design which
dramatically improves accuracy. This monolithic device is constructed
using an advanced high-performance bipolar process.
The CLC532 has been specifically designed to provide settling times
of 17ns to 0.01%. This, coupled with the adjustable noise-bandwidth,
makes the CLC532 an ideal choice for infrared and CCD imaging
systems. Channel-to-channel isolation is better than 80dB @
10MHz. Low distortion (80dBc) and spurious signal levels make the
CLC532 a very suitable choice for both I/Q processors and receivers.
The CLC532 is offered over both the industrial and military temperature
ranges. The Industrial versions, CLC532AJP\AJE\AID, are specified
from -40°C to +85°C and are packaged in 14-pin plastic DIP's, 14-pin
SOIC's and 14-pin Side-Brazed packages. The extended temperature
versions,CLC532A8B/A8D/A8L-2,arespecifiedfrom-55°Cto+125°C
and are packaged in a 14-pin hermetic DIP and 20-terminal LCC
packages. (Contact factory for LCC and CERDIP availability.)
Ordering Information ...
CLC532AJP
-40oC to +85oC
14-pin plastic DIP
CLC532AJE
-40oC to +85oC
14-pin plastic SOIC
CLC532ALC
-40oC to +85oC
dice
CLC532AMC
-55oC to +125oC dice, MIL-STD-833
CLC532A8B
-55oC to +125oC 14-pin CERDIP;
MIL-STD-883
CLC532A8L-2A -55oC to +125oC 20-terminal LCC;
MIL-STD-883
Contact factory for other packages and DESC SMD number.
Features
s 12-bit settling (0.01%) - 17ns
s Low noise - 32µVrms
s High isolation - 80dB @ 10MHz
s Low distortion - 80dBc @ 5MHz
s Adjustable bandwidth - 190MHz (max)
Applications
s Infrared system multiplexing
s CCD sensor signals
s Radar I/Q switching
s High definition video HDTV
s Test and calibration
Typical Application
CHANNEL A
RIN
CHANNEL B
RIN
2
1
INA
CCOMP1
12
11
CLC532
4
3
INB
7
6
10
DREF
VOUT
RL
CCOMP2
CHANNEL
SELECT
SELECT OUTPUT
1 Channel A
0 Channel B
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
20-Terminal LCC
Pinout
DIP & SOIC
87654
DREF 9
SELECT 10
NC 11
VEE 12
VEE 13
TOP VIEW
14 15 16 17 18
INDEX CORNER
3 INA
2 GND
1 NC
20 +Vcc
19 +Vcc
GND
INA
GND
INB
DGND
DREF
SELECT
1
2
3
4
5
6
7
14 +VCC
13 +VCC
12 COMP1
11 OUTPUT
10 COMP2
9 VEE
8 VEE
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CLC532AJP Datasheet, Funktion
Applications Information
Operation
The CLC532 is a 2:1 analog multiplexer with high-impedance
buffered inputs, and a low-impedance, low-distortion, output
stage. The CLC532 employs a closed-loop design, which
dramatically improves accuracy. The channel SELECT control
(Figure 1) determines which of the two inputs (IN or IN ) is
AB
present at the OUTPUT. Beyond the basic multiplexer function,
the CLC532 offers compatibility with either TTL or ECL logic
families, as well as adjustable bandwidth.
TTL CMOS
R3 6203.6k
R2 200510
R1 510680
+5V
CHANNEL
SELECT
A/B
R3
R2
R1
CLC532
7
6
DREF
+5V
+5V Figure 3: TTL/CMOS Level Channel SELECT Configuration
+6.8 µ F
0.1 µ F
CHANNEL A
RIN
CHANNEL B
RIN
CHANNEL
SELECT
2
1
INA
13
14
12
CCOMP1
CLC532 11
4
3
INB
5 78
DGND
9
6
10
DREF
RL
CCOMP2
VOUT
+6.8 µ F
0.1µF
Compensation
The CLC532 incorporates compensation nodes that allow both
its bandwidth and its settling time/slew rate to be adjusted.
Bandwidth and settling time/slew adjustments are linked,
meaning that lowering the bandwidth also lowers slew rate
and lengthens settling time. Proper adjustment (compensation)
is necessary to optimize system performance. Time Domain
applications should generally be optimized for lowest RMS
noise at the CLC532 output, while maintaining settling time and
slew rates at adequate levels to meet system needs. Frequency
Domain applications should generally be optimized for maximally
flat frequency response.
Figure 4 below describes the basic relationship between
bandwidth and R for various values of load capacitance, C ,
SL
where C = 10pF.
COMP
-5.2V
Figure 1: Standard CLC532 Circuit Configuration
Digital Interface and Channel SELECT
The CLC532 functions with ECL, TTL and CMOS logic families.
DREF controls logic compatibility. In normal operation, DREF is left
floating, and the channel SELECT responds to ECL level signals,
Figure 2. For TTL or CMOS level SELECT inputs (Figure 3), DREF
should be tied to +5V (the CLC532 incorporates an internal
2300series isolation resistor for the DREF input). For TTL or
CMOS operation, the channel SELECT requires a resistor input
network to prevent saturation of the channel select circuitry.
Without this input network, channel SELECT logic levels above
3V will cause internal junction saturation and slow switching
speeds.
100
90
80
70 R s
60
50
40
30
Ts
20
0.01%
10
0.05%
0
1
Rs
CL
2V Output Step
1k
100
CL (pF)
100
90
80
70
60
50
40
30
20
10
0
1000
Figure 4: Settling Time and RS vs. CL
Figure 5 shows the resulting changes in bandwidth and slew rate
for increasing values of C . The RMS noise at the CLC532
COMP
output can be approximated as:
OUTPUTNOISERMS = (nV)(1.57*BW-3dB)
CHANNEL
SELECT
A/B
ECL GATE
50
CLC532
6
7
SELECT
DREF
(NC)
Thevinen Equivalent
Output Termination
50
-2V
R1
To ECL
Gate
81
To
SELECT
R2 130
-5.2V
where... n = input spot noise voltage;
V
BW = Bandwidth is from figure 5.
-3dB
200
180
160
140
120
100
80
60
40
20
0
1
-3dB Bandwidth
10
Ccomp (pF)
Slew Rate
200
180
160
140
120
100
80
60
40
20
100
Figure 2: ECL Level Channel SELECT Configuration
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Figure 5: C for Maximally Flat Frequency Response
COMP
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CLC532AJP pdf, datenblatt
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of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
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Tel: 81-043-299-2309
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
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