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CLC427 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC427
Beschreibung Dual Voltage Feedback Amplifier for Single Supply Operation
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 8 Seiten
CLC427 Datasheet, Funktion
N
Comlinear CLC427
Dual Voltage Feedback Amplifier
for Single Supply Operation
General Description
The Comlinear CLC427 is a dual wideband voltage-feedback
operational amplifier that is uniquely designed to provide high
performance from a single power supply. This CLC427 provides
near rail-to-rail operation and the common-mode input range
includes the negative rail. Each of the CLC427’s amplifiers offers
plenty of headroom for single-supply applications as evidenced
by its 4.3Vpp output voltage from a single 5V supply.
Fabricated with a high-speed complementary bipolar process,
the CLC427 delivers a wide 94MHz unity-gain bandwidth, 7.5ns
rise/fall time and 150V/µs slew rate. For single supply applications
such as video distribution or desktop multimedia, the CLC427
offers low 0.35%, 0.55° differential gain and phase errors.
Each of the CLC427’s amplifiers provides high signal fidelity
with -74/-94dBc 2nd/3rd harmonics (1Vpp, 1MHz, RL=150).
Combining this high fidelity performance with CLC427’s quick
46ns settling time to 0.1% makes it an excellent choice for ADC
buffering.
With its traditional voltage-feedback architecture and high-speed
performance, the CLC427 is the perfect choice for composite
signal conditioning circuit functions such as active filters,
integrators, differentiators, simple gain blocks and buffering.
August 1996
Features
s Single +5V supply
s Input includes VEE
s 94MHz unity-gain bandwidth
s -74/-94dBc HD2/HD3
s 60mA output current
s 7.5ns rise/fall time (1Vpp)
s 46ns settling time to 0.1%
Applications
s Video ADC driver
s Desktop multimedia
s Single supply cable driver
s Instrumentation
s Video cards
s Wireless IF amplifiers
s Telecommunications
Frequency Response vs. Vout
Av = +2V/V
1Vpp
2Vpp
4Vpp
Typical Application
Single +5V Supply operation
Vin
50
+5V
0.1µF
+
1/2
CLC427
-
6.8µF +
150
Vo
250
250
NOTE: Vin = 0.15V to 2.3V
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
1 10 100
Frequency (MHz)
Single Supply Response
VCC 5
4
3
2
1
VEE 0
Time (100ns/div)
Pinout
DIP & SOIC
Vo1
Vinv1
Vnon-inv1
VEE
VCC
Vo2
Vinv2
Vnon-inv2
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CLC427 Datasheet, Funktion
The maximum power that the package can dissipate at a
given temperature is illustrated in the Power Derating
curves in the Typical Performance section. The power
derating curve for any package can be derived by
utilizing the following equation:
(175° − Tamb )
θJA
where: Tamb = Ambient temperature (°C)
θJA = Thermal resistance, from junction to
ambient, for a given package (°C/W)
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides evalu-
ation boards for the CLC427 (730038 - DIP, 730036-
SOIC) and suggests their use as a guide for high
frequency layout and as an aid for device testing and
characterization.
General layout and supply bypassing play major roles in
high frequency performance. Follow the steps below as
a basis for high frequency layout:
1. Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
2. Place the 6.8µF capacitors within 0.75 inches
of the power pins.
3. Place the 0.1µF capacitors within 0.1 inches
of the power pins.
4. Remove the ground plane under and around
the part, especially near the input and output
pins to reduce parasitic capacitance.
5. Minimize all trace lengths to reduce series
inductances.
Additional information is included in the evaluation board
literature.
Applications Circuits
Typical Application Circuit
The typical application shown on the front page illustrates
the near rail-to-rail performance of the CLC427.
Multiple Feedback Bandpass Filter
Figure 9 illustrates a bandpass filter and design
equations. The circuit operates from a single supply of
+5V. The voltage divider biases the non-inverting input to
2.5V. The input is AC coupled to prevent the need for
level shifting the input signal at the source. Use the
design equations to determine R1 and R2 based on the
desired Q and center frequency.
This example illustrates a bandpass filter with Q = 4 and
center frequency fc = 1MHz. Figure 10 indicates the
filter response.
+5V
6.8µF
+
5.1k
3(5) + 8 0.1µF
Vin
R1
5.1k
C
1/2 1(7)
2(6)
CLC427
-
4 R2
50390pF C 3.16k
R2
=
Q
πfrc
R1
=
R2
4Q2
fr = resonant frequency 390pF
A = 2Q2 A = midband gain
Figure 9: Bandpass Filter Topology
Vo
40
30.6dB
940kHz
30
20
10
0
-10
1 10
Frequency (MHz)
Figure 10: Bandpass Response
Distribution Amplifier
Figure 11 illustrates a distribution amplifier. The topology
utilizes the dual amplifier package. The input is
AC coupled and the non-inverting terminals of both
amplifiers are biased at 2.5V.
+5V
6.8µF
+
Vin CC R
Ro R
3(5) + 8 0.1µF
1/2 1(7)
2(6)
CLC427
-
Rf
Rg
C
Ro
Zo
Vo1
Ro
3(5) +
1/2 1(7)
2(6)
CLC427
-
4 Rf
Rg
C
Ro
Zo
Vo2
Ro
Figure 11: Distribution Amplifier
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