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CLC407AJ Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC407AJ
Beschreibung Low-Cost/ Low-Power Programmable Gain Buffer with Disable
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 8 Seiten
CLC407AJ Datasheet, Funktion
August 1996
N
Comlinear CLC407
Low-Cost, Low-Power
Programmable Gain Buffer with Disable
General Description
The Comlinear CLC407 is a low-cost, high-speed (110MHz)
buffer which features user-programmable gains of +2, +1, and -1
V/V. This high-performance part has the added versatility of a
TTL-compatible disable which quickly switches the buffer off in
18ns and back on in 40ns. The CLC407’s high 60mA output
current, coupled with its ultra-low 35mW power consumption
makes it the ideal choice for demanding applications that are
sensitive to both power and cost.
Utilizing Comlinear’s proven architectures, this current feedback
amplifier surpasses the performance of alternate solutions with a
closed-loop design that produces new standards for buffers in
gain accuracy, input impedance, and input bias currents. The
CLC407’s internal feedback network provides an excellent gain
accuracy of 0.1%. High source impedance applications will
benefit from the CLC407’s 6Minput impedance along with its
exceptionally low 100nA input bias current.
With 0.1dB flatness to 30MHz and low differential gain and phase
errors, the CLC407 is very useful for professional video process-
ing and distribution. A 110MHz -3dB bandwidth coupled with a
350V/µs slew rate also make the CLC407 a perfect choice in
cost-sensitive applications such as video monitors, fax machines,
copiers, and CATV systems. Back-terminated video applications
will especially appreciate +2 gains which require no external gain
components reducing inventory costs and board space.
Features
s Low-cost
s High output current: 60mA
s High input impedance: 6M
s Gains of +1, +2 with no external components
s Low power: Icc = 3.5mA
s Ultra-fast enable/disable times
s Very low input bias currents: 100nA
s Excellent gain accuracy: 0.1%
s High speed: 110MHz -3dB BW
Applications
s Desktop video systems
s Multiplexers
s Video distribution
s Flash A/D driver
s High-speed switch/driver
s High-source impedance applications
s Peak detector circuits
s Professional video processing
s High resolution monitors
Frequency Response (AV = +2V/V)
Typical Application
2:1 Mux Cable Driver
NOTE: All necessary components are shown.
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
Pinout
DIP & SOIC
http://www.national.com






CLC407AJ Datasheet, Funktion
Use power-supply bypassing capacitors when
operating this amplifier. Choose quality 0.1µF ceramics
for C1 and C2. Choose quality 6.8µF tantalum capacitors
for C3 and C4. Place the 0.1µF capacitors within 0.1
inches from the power pins. Place the 6.8µF capacitors
within 3/4 inches from the power pins.
Special Evaluation Board
Considerations for the CLC407
To optimize off-isolation of the CLC407, cut the Rf trace on
both the 730013 and the 730027 evaluation boards. This
cut minimizes capacitive feedthrough between the input
and the output. Figure 4 shows where to cut both evalu-
ation boards for improved off-isolation.
730013
REV C
OUT
C1 C6
+
C5
+
C2
C8
R5
R8
RF
Comlinear
C7
A National Semiconductor Company
-Vcc GND +Vcc
IN
(303) 226-0500
Cut trace here Cut trace here
Figure 4
407 Fig 3 (Right)
Video Performance vs. IEX
Improve the video performance of the CLC407 by drawing
extra current from the amplifier’s output stage. Using a
single external resistor as shown in Figure 5, you can
adjust the differential phase. Video performance vs. IEX is
illustrated below in Graph 2. This graph represents
positive video performance with negative synchronization
pulses.
Differential Gain & Phase vs. IEX
0.25
0.25
0.20
Phase
0.15
0.20
0.15
0.10 0.10
J1 = 0
SMA
Input
Rin
50
18
+5V
2
7 C1
C3 +
3 6 0.1µfd 6.8µfd
CLC407
Rout
SMA
4 5 50Output
Rpd IEX
C2 C4
0.1µfd 6.8µfd +
-5V
Figure 5
Video Cable Driver
The CLC407 was designed to produce exceptional video
performance at all three closed-loop gains. At the non-
inverting gain of 2V/V configuration, back terminate the
cable using Rout. A typical cable driving configuration is
shown below in Figure 6.
J1 = 0
1
2
SMA
Input
Rin
50
3
CLC407
4
C2 C4
0.1µfd 6.8µfd
8
7 C1
6 0.1µfd
Rout
5 50
-5V
+
C3
6.8µfd
Coax
50
+5V
+
Video
Output
50
Figure 6
N:1 Mux Cable Driver
The CLC407 is capable of multiplexing several signals on a
single analog output bus. The front page shows how a 2:1
multiplexer is implemented. An N:1 multiplexer is implement-
ed in an analogous fashion by using an N:1 decoder to
enable/disable the appropriate number of CLC407’s.
Package Thermal Resistance
Package
Plastic (AJP)
Surface Mount (AJE)
CerDip
qjc
75˚/W
130˚/W
65˚/W
qjA
125˚/W
150˚/W
155˚/W
0.05
0
0
0.05
Gain
0
2 4 6 8 10 12 14 16 18
IEX in mA
Graph 2
405 G h1
The value for Rpd in Figure 5 is determined by:
at +5V supplies.
Rpd
=
5
IEX
Ordering Information
Model
Temperature Range
Description
CLC407AJP
CLC407AJE
CLC407AIB
CLC407ALC
CLC407A8B
CLC407AMC
-40˚C to +85˚C
-40˚C to +85˚C
-40˚C to +85˚C
-40˚C to +85˚C
-55˚C to +125˚C
-55˚C to +125˚C
8-pin PDIP
8-pin SOIC
8-pin CerDIP
dice
8-pin CerDIP, MIL-STD-883
dice, MIL-STD-883
Contact factory for other packages and DESC SMD number.
http://www.national.com
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