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CLC021AVGZ-3.3 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CLC021AVGZ-3.3
Beschreibung SMPTE 259M Digital Video Serializer with EDH Generation and Insertion
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 18 Seiten
CLC021AVGZ-3.3 Datasheet, Funktion
July 2003
CLC021
SMPTE 259M Digital Video Serializer with EDH
Generation and Insertion
General Description
The CLC021 SMPTE 259M Digital Video Serializer with EDH
Generation and Insertion is a monolithic integrated circuit
that encodes, serializes and transmits bit-parallel digital data
conforming to SMPTE 125M and 267M component video
and SMPTE 244M composite video standards. The CLC021
can also serialize other 8- or 10-bit parallel data. The
CLC021 operates at data rates from below 100 Mbps to over
400 Mbps. The serial data clock frequency is internally gen-
erated and requires no external frequency setting, trimming
or filtering components*.
Functions performed by the CLC021 include: parallel-to-
serial data conversion, ITU-R BT.601-4 input data clipping,
data encoding using the SMPTE polynomial (X9+X4+1), data
format conversion from NRZ to NRZI, parallel data clock
frequency multiplication and encoding with the serial data,
and differential, serial output data driving. The CLC021 has
circuitry for automatic EDH character and flag generation
and insertion per SMPTE RP-165. The CLC021 has an
exclusive built-in self-test (BIST) and video test pattern gen-
erator (TPG) with 16 component video test patterns: refer-
ence black, PLL and EQ pathologicals and modified colour
bars in 4:3 and 16:9 raster formats for NTSC and PAL
formats*.
The CLC021 has inputs for enabling sync detection, non-
SMPTE mode operation, enabling the EDH function, NRZ/
NRZI mode control and an external reset control. Outputs
are provided for H, V and F bits, new TRS sync character
position indication, ancilliary data header detection, NTSC/
PAL raster indication and PLL lock detect. Separate power
pins for the output driver, VCO and the serializer improve
power supply rejection, output jitter and noise performance.
The CLC021AVGZ-5.0V is powered by a single +5V supply.
The CLC021AVGZ-3.3V is powered by a single +3.3V sup-
ply. Power dissipation is typically 235 mW including two 75
back-matched output loads. The device is packaged in a
JEDEC metric 44-lead PQFP.
Features
n SMPTE 259M serial digital video standard compliant
n Supports all NTSC and PAL standard component and
composite serial video data rates
n No external serial data rate setting or VCO filtering
components required*
n Fast VCO lock time: <75 µs at 270 Mbps
n Built-in self-test (BIST) and video test pattern generator
(TPG) with 16 internal patterns*
n Automatic EDH character and flag generation and
insertion per SMPTE RP 165
n Non-SMPTE mode operation as parallel-to-serial
converter
n NRZ-to-NRZI conversion control
n HCMOS/LSTTL-compatible data and control inputs and
outputs for CLC021AVGZ-5.0, LVCMOS for
CLC021AVGZ-3.3
n 75ECL-compatible, differential, serial cable-driver
outputs
n Single power supply operation: 5V (CLC021AVGZ-5.0)
or 3.3V (CLC021AVGZ-3.3) in TTL or ECL systems
n Low power: typically 235 mW
n JEDEC 44-lead metric PQFP package
n Commercial temperature range 0˚C to +70˚C
* Patents applications made or pending.
Applications
n SMPTE 259M parallel-to-serial digital video interfaces
for:
— Video cameras
— VTRs
— Telecines
— Video test pattern generators and digital video test
equipment
— Video signal generators
n Non-SMPTE video applications
n Other high data rate parallel/serial video and data
applications
Typical Application
© 2003 National Semiconductor Corporation DS101368
10136812
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CLC021AVGZ-3.3 Datasheet, Funktion
AC Electrical Characteristics—CLC021AVGZ-3.3 (Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min Typ Max
Units
LGEN
RGEN
Output Inductance
Output Resistance
(Note 4)
(Note 4)
SDO, SDO
6 nH
25k
Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics”
specifies acceptable device operating conditions.
Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VSS = 0V.
Note 3: Typical values are stated for VDD = +5.0V (CLC021AVGZ-5.0) or +3.3V (CLC021AVGZ-3.3) and TA = +25˚C.
Note 4: Specification is guaranteed by design.
Note 5: RL = 75, AC-coupled @ 270 Mbps, RREF = 1.69 k1%, See Test Loads and Figure 2.
Note 6: CLC021 mounted in the SD021EVK board, configured in BIST mode (NTSC colour bars) with PCLK = 27 MHz derived from Tektronix TG2000 black-burst
reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1 kHz filter bandwidth, Hanning window.
Note 7: Measured from rising-edge of first PCLK cycle until Lock Detect output goes high (true).
Test Loads
FIGURE 1. Test Loads
10136803
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CLC021AVGZ-3.3 pdf, datenblatt
Device Operation (Continued)
TABLE 1. BIST and Test Pattern Generator Control Functions
Pin Name
Function
12 D0 TPG Code Input LSB
13 D1 TPG Code Input
14 D2 TPG Code Input
15 D3 TPG Code Input MSB
29 TPG_EN TPG Enable, Active High True
3 Test_Out BIST Pass/Fail Output. Pass=High
(See text for Timing Requirements)
TABLE 2. Component Video Test Pattern Selection
Standard Frame
Test Pattern
NTSC
4x3 Flat-Field Black
NTSC
4x3 PLL Pathological
NTSC
4x3 EQ Pathological
NTSC
4x3 Colour Bars, 75%, 8-Bars (modified, see text), BIST
PAL 4x3 Flat-Field Black
PAL 4x3 PLL Pathological, BIST
PAL 4x3 EQ Pathological
PAL 4x3 Colour Bars, 75%, 8-Bars (modified, see text)
NTSC
16x9 Flat-Field Black
NTSC
16x9 PLL Pathological
NTSC
16x9 EQ Pathological
NTSC
16x9 Colour Bars, 75%, 8-bars (modified, see text)
PAL 16x9 Flat-Field Black
PAL 16x9 PLL Pathological
PAL 16x9 EQ Pathological
PAL 16x9 Colour Bars, 75%, 8-Bars (modified, see text)
Note: D9 through D4 = 0 (binary)
D3 D2 D1 D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
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